l4969 STMicroelectronics, l4969 Datasheet - Page 19

• Manufacturer Part Number: l4969
• Description: System Voltage Regulator With Fault Tolerant Low Speed Can-transceiver
• Manufacturer: STMicroelectronics

2
The functionality of the device can be observed and controlled through a set of registers which are read and
writable by the serial interface.
2.1
Note, that when using the Undervoltage-detection, EUV2 and EUV3 have to be activated AFTER V2 or V3 have
been turned on and settled (t > 1ms). Otherwise unwanted undervoltage can be detectected during turn on of
the corresponding voltage regulator.
Set reset threshold value to 4.0V
Default value is ‘0’ (4.5V)
Enable undervoltage
Regulator #2 and #3
(see note below)
Enable Regulator #3 .
V3 will be activated by either setting ENV3 or
upon enabling of the CAN Lineinterface
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature from CANIF or Regulator #3
Enable Regulator #2 tracking option
to have V2 following V1 with constant offset
Default value is ‘0’ (disabled)
V1
EUV3
D7
DISAR
CONTROL AND STATUS REGISTERS
detection on
ADR 0: VRCR Voltage Regulator Control Register
EUV2
RTC0
Note, that due to the large initial charging current of the output capacitors,
the activation of V2 AND V3 within the same command is not recommended
also leaving ENV2 or ENV3 set when setting DISAR can therefor not be
recommended (after wakeup V1 AND V2 or V3 would be turned on)
REF
TRC
TRC
written as ‘0’.
Has to be
RES
ENV3
DISAR & ENV2
ENV2
V2
Enable Regulator #2.
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature at Regulator #2.
V3 will be activated upon VRCR.ENV3 or
CCTR.ACT without pending thermal shutdown
This bit will be automatically set upon
the system failures Overtemperature V1
or watchdog startup failure.
Disable all Regulators (Go to Sleep)
Note, that at least one Wakeup Source
without a pending wakeup is required
to enable access.
Note, that no reset will be generated
from low V1 during Sleep mode transition
The Reset line has to be forced low
externally, or through a window failure
DISAR will be cleared upon a valid
wakeup signal which is either defined
in GIEN or is forced to WAKE or CAN
after a system failure
DISAR
D0
(DISAR & ENV3 |
ACT) & TSDV3
V3
L4969
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