l4969 STMicroelectronics, l4969 Datasheet
l4969
Available stocks
Related parts for l4969
l4969 Summary of contents
Page 1
... This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. SYSTEM VOLTAGE REGULATOR SO20 ORDERING NUMBERS: L4969MD (SO20) DESCRIPTION The L4969 is an integrated circuit containing 3 inde- pendent Voltage Regulators and a standard fault tol- erant low speed CAN line interface in multipower BCD3S process. It integrates all main local functions for automotive body electronic applications connected to a CAN bus ...
Page 2
... L4969 Figure 2. Pin Connection GND PSO20 CANH RTL CANL RTH GND Table 1. Pin Functions Pin No. (PSO20) Pin No. (SO20) 1, 10, 11, 20 5,6, 15 Table 2. Thermal Data ...
Page 3
... S I >-100mA O SO20 Package 6V < V < 28V S I >-150mA O PSO20 Package I = -10mA OUT1 I = -100mA OUT1 SO20 Package I = -150mA OUT1 PSO20 Package L4969 Value Unit -0.3 ... +28 V -0.3 ... +40 V Internally limited -65 ... +150 °C -40 ... +150 °C -0.3 ... VS+0.3, max +6.3 V -0.3 ... VS+0.3 V -0.3 ... VS+0.3, max +6.3 V -0.3 ... +7 V -0.3 ... VS+0.3 V -28 ... +40 V -28 ... +40 V Min ...
Page 4
... L4969 Table 4. Electrical Characteristics (continued 14V -40°C to 150°C unless otherwise specified Symbol Parameter V Load regulation 1 OL01 I Current limit 1 LIM1 V Line regulation 1 OLI1 T Overtemp flag 1 OVT1 T Thermal shutdown 1 OTKL1 V Min V1 reset threshold voltage RTC0 = 0 res Voltage Regulator 2 and 3 V Output voltage ...
Page 5
... RES I = 500u 1.5V RES C = 3.3nF load C = 3.3nF, load R =100 TERM 10% ... 90 3.3nF Load min V to turn off CAN-IF and 0.9 No bus failures No bus failures L4969 Min. Typ. Max. Unit 1 t WDC 2 t WDC 4 t WDC 8 t WDC 2 t WDC 4 t WDC 8 ...
Page 6
... L4969 Table 4. Electrical Characteristics (continued 14V -40°C to 150°C unless otherwise specified Symbol Parameter V CANH recessive output CANHr voltage V CANH dominant output CANHd voltage V CANL recessive output CANLr voltage V CANL dominant output CANLd voltage I CANH dominant output CANH current ...
Page 7
... dom to rec edges to EdgeHR detect recovery of CANH Test Conditions 0.9 RXD = 0 RXD = 5V SOUT = 0 SOUT = 5V INT = 0 INT = 5V RESET = 0 RESET = Wake Wake Operating mode (EI_V) Operating mode (EI_V) L4969 Min. Typ. Max. Unit 0 0 0.9 V 4 ...
Page 8
... L4969 Table 4. Electrical Characteristics (continued 14V -40°C to 150°C unless otherwise specified Symbol Parameter dom to rec edges on EdgeL CANH to detect permanent rez CANL dom to rec edges to EdgeLR detect recovery of CANL t CANH to V short circuit EIII S detection time ...
Page 9
... FUNCTIONAL DESCRIPTION 1.1 General Features The L4969 is a monolithic integrated circuit which provides all main functions for an automotive body CAN network. It features two independent regulated voltage supplies V1 and V2, an interrupt and reset logic with internal clock generator, Serial Interface and a low speed CAN-bus transceiver which is supplied by a separate third voltage regulator (V3) ...
Page 10
... L4969 1.2 Power-Up, Initialization and Sleep mode transitions The following state-diagram illustrates the possible mode transitions inside the device prerequisite, a SPI-connection to the uC with the correct CRC-algorythms is required. During the debug phase the NRES line can be forced high externally (connect to V1) to deactivate the startup failure mechanis keeping V1 will alive ...
Page 11
... CANH, CANL driven dominant for more than 1.3ms Not all of the 10 different errors lead to a breakdown of the whole communication. So the errors can be categorized into 'negligible', 'problematic' and 'severe': (overvoltage condition) L4969 Conditions Edgecount difference > 3 Edgecount difference > 3 V(CANH) > 7.2V after 32us V(CANL) < ...
Page 12
... L4969 1.3.2 Negligible Errors 1.3.2.1 Transmitter Error I and II (CANH or CANL interrupted but still tied to termination) Error IV and VIII (CANH or CANL permanently dominant by short circuit) In all cases above data can still be transmitted in differential mode. 1.3.2.2 Receiver Error I and II (CANH or CANL interrupted but still tied to termination) Error V and IX (CANH or CANL permanently recessive by short circuit) In all cases above data can still be received in differential mode ...
Page 13
... Standby #3: off V3 off,CAN-Standby mode, ID-Filter disabled, Startup Watchdog active With VS below 5V the regulator V1 will follow VS with minimum drop. The C retrieves a reset dropping below a programmable voltage level of either 4.5V (default) or 4.0V. The programmed state of the L4969 re- mains unchanged. The act. low Resetpulse duration is fixed internally by an open-drain output stage to 1ms. ...
Page 14
... With Timer (WDEN=1): immediately after setting DISAR the uC has to program its WDC to generate a failure causing the L4969 to detect a low level on NRES followed by an automatic 1ms pulse extension ramping down slow, Cext has to be defined in a way, that NRES will stay below the input threshold of the uC until safe level ...
Page 15
... Serial Interface (SPI) A standard serial peripheral interface (SPI) is implemented to allow access to the internal registers of the L4969. A total of 12 Registers with different datalengths can be directly read from or written to, providing the requested address at the beginning of a dataframe. Upon every access to this interface, the content of the register currently accessed is shifted out via SOUT ...
Page 16
... L4969 1.10.2 Address/Command Field ADR3 Frame start sequence always has to be transmitted The Address/Command field starts with a 2-Bit start sequence consisting of ‘01’. Any other sequence will lead to a protocol error signalled via the NINT. The addressfield is specifying the register to be accessed. The SPI command flags allow in addition to the normal read/write operation to clear the Interrupt flag register after read ...
Page 17
... CRC to address 15. CRC-checking will be reenabled upon another operation of this kind (Toggled information CRC3 CRC2 CRC Check sequence to be appended to tranferred data Note that upon CRC check failure no write operation will be performed SIN: CRC of SIN sequence SOUT: CRC of SOUT sequence CRC1 CRC0 L4969 17/34 ...
Page 18
... L4969 1.11 Memory Map Table 5. L4969 Memory Map ADR Group MSB D10 0 VRCR 1 CTCR 2 GPTR Undefined Register Memory 3 RCADJ 4 WDC 5 GIEN 6 IFR ESPI ISET IRES 7 CTSR RES RES RES 8 ID01 A11 A10 A01 9 ID23 D11 D10 D01 10 BTL PS23 PS22 PS21 11 NAV ...
Page 19
... GIEN or is forced to WAKE or CAN after a system failure Enable Regulator #2. Default value is ‘0’ (disabled) This bit will be automatically reset upon Overtemperature at Regulator #2. (DISAR & ENV3 | ACT) & TSDV3 V3 V3 will be activated upon VRCR.ENV3 or CCTR.ACT without pending thermal shutdown L4969 19/34 ...
Page 20
... L4969 2.2 ADR 1: CTCR CAN-Transceiver Control Register D7 ACT TXEN RES CAN-Transceiver application control 0X : Standby / Sleep 10 : Receive only mode A (Readback TX, if not EX Normal Operation Note, that TXEN is automatically reset upon occurence of EX (TX permanent dominant) and has to be reprogrammed after problem correction to enter normal mode. ...
Page 21
... No request (Adjustment disabled) 01: 2.5ms low cycle on NINT (repetitive) 10: Finish cycle measurement 11: No request (Adjustment disabled) D0 TM0 TMUX TEN D0 ADJ0 -1% RC Oscillator Frequency Adjust default value 10000 Note, that programming is only enabled with PGEN set L4969 21/34 ...
Page 22
... L4969 State transition during oscillator calibration CG=01 “No Request” Start time measurement Watchdog and Interrupt has to be disabled 2.5 ADR4: WDC Watchdog Control Register D7 WDEN WND Disable Window Watchdog, only allowed with PGEN set, see previous table for Osc adjust Enable Wakeup Watchdog, ...
Page 23
... NRESET No Startup Acknowledgement via SPI within 2.3s (Device will enter Sleep mode) After powerup, the L4969 is expecting the uC to send an acknowledgement within a predefined segmented tim- ing frame 320ms. A missing acknowledgement until after the 2.3s will force the device into sleep mode until either external or CAN wakeup or POR cause a restart of the sequence above. ...
Page 24
... L4969 2.5.4 Wakeup Watchdog Window Wd Ack Window & Start Timer NINT Interrupt active upon timeout (via GIEN) If the Timer is activated during Normal mode by setting WDEN in WDC, an “acknowledge-free” sequence is started for a predefied programmable time. Window Watchdog activity is resumed after expiry of the timer. ...
Page 25
... Warning level reached OVT1 : T(V1) > 140degC OVT2 : T(V2) > 140degC OVT3 : T(V3) > 140degC D0 EIFW Enable Identifier based wakeup / Interrupt Enable Wakeup,/ Interrupt via Watchdog WKE WKC WKW Signal edge on WAKE detected Wakeup condition via CAN detected Watchdog timeout detected Identifier passed CAN ID-Filter L4969 D0 WKIF 25/34 ...
Page 26
... L4969 2.8 ADR7: CTSR CAN Transceiver Status Register D11 RES RES RES GSH CANH < -1V at falling edge TX TX permanent dominant detected CANH permanent dominant detected Short circuit CANH to CANL detected Reserved bits (‘RES’) are always read as ‘0’ Note, that this register is read only and only provides the unlatched information on current buserrors. ...
Page 27
... SEGB: B01 SEGC: C01, C00 SEGD: D10, D01 SEGE: E11, E01, E00 1011 ID01: 0110 1011 0110 SEGF: F10, F01 SEGE SEGF ID2 ID1 ID0 RTR 4/2 Demux 11 PASS ID bits to be set 0101 0010 ID01: 0011 0010 0101 0011 0110 0011 L4969 27/34 ...
Page 28
... L4969 2.10 ADR 10: BTL Identifier Filter Bittimelogic Control Register D11 PS23 PS22 PS21 PS2 Phasesegment 2 length configuration t = 1us * PSEG2 PSEG2 99AT0030 The total bitlength equals the sum PSEG1 + PSEG2 in units of s. The location of the sampling point is determined by the length of PSEG1. At the start of frame (initial recessive to dominant edge) the bitlength counter is reset. ...
Page 29
... Watchdog-Acknowldge, and will then be reinitialized to 000001. WNDF STF OTF UCF Warm start after V1 Overtemp failure Warm start after 7 missing Ack during Startup Warm start after < 7 missing Ack during Startup L4969 D0 WAKE NPOR Cold Start after low VS Warm start after leaving prog. Sleep mode 29/34 ...
Page 30
... L4969 3 INTERRUPT MANAGEMENT D11 ESPI ISET IRES UV23 NINT All Interrupt flags (in IFR) except ESPI can be masked in the global interrupt enable register (GIEN). An Interrupt will be signalled by NINT going low until either the corresponding mask or the flag itself will be reset by the application software. An autoreset function is available for IFR, allowing to remove all interrupt flags after reading their state (see SPI) ...
Page 31
... WAKE V3 * 33u 47n RTH * 47p CANH CANL * 47p RTL 99AT0032 * C ceramic C close to pin recommended for EMI Thermal Supervision V2 V1 120K NRES NINT SCLK SPI SOUT CAN Transceiver Groundshift Detection ID-Filter GND L4969 Peripheral Supply * 10u 47n * 10u 47n opt C SIN RX TX 31/34 ...
Page 32
... L4969 mm DIM. MIN. TYP. MAX. MIN. A 2.35 2.65 0.093 A1 0.10 0.30 0.004 B 0.33 0.51 0.013 C 0.23 0.32 0.009 (1) 12.60 13.00 0.496 D E 7.40 7.60 0.291 e 1.27 H 10.0 10.65 0.394 h 0.25 0.75 0.010 L 0.40 1.27 0.016 k 0˚ (min.), 8˚ (max.) ddd 0.10 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed ...
Page 33
... A e DETAIL B 11 BOTTOM VIEW PSO20MEC OUTLINE AND MECHANICAL DATA JEDEC MO-166 PowerSO20 DETAIL A lead slug a3 DETAIL B 0.35 Gage Plane - SEATING PLANE (COPLANARITY L4969 0056635 33/34 ...
Page 34
... L4969 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...