adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 55

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adau1361

Manufacturer Part Number
adau1361
Description
Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
Manufacturer
Analog Devices, Inc.
Datasheet

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R14: ALC Control 3 16404 (0x4014)
Bit 7
Table 41. ALC Control 3 Register
Bit
[7:6]
5
[4:0]
R15:
Bit 7
DITHEN
Table 42. Serial Port Cont
Bit
7
5
4
3
[2:1]
Ser
ial Port Cont
Bit Name
NGTYP[1:0]
NGEN
NGTHR[4:0]
NGTYP[1:0]
Bit
DITHEN
LRMOD
BPOL
LRPOL
CHPF[1:0]
Name
Bit 6
Bit 6
Reserved
rol
D
Dither enable is applicable only f
0
1 = enabled.
LRCLK mode can set the LRCLK fo
w
0 = 50% duty cycle (default).
1 = pulse mode.
BCLK polarity sets the BCLK edge
of the BCLK.
0 = falling edge (default).
1
LRCLK polarity sets the LRCLK ed
f
0 = falling edge (default).
1
Channels per frame sets the number of channels per LRCLK frame.
Setting
00
01
10
11
0 16405 (0x4015)
rol 0 R
or the f
Description
Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant
PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.
Setting
00
01
10
11
Noise
0 = dis
1 = en
Noise gate threshold. When the
A 1 LS
Setting
00000
00001
11110
11111
escrip
= disa
ide.
= risin
= risin
gate enable.
B increase corresponds to
abled.
bled (default).
abled (default).
egister
g edge.
alling or rising edge of th
g edge.
tion
Bit 5
NGEN
Bit 5
LRMOD
Bit 4
Bit 4
BPOL
or 16-b
ge that trig
e LRCLK.
Noise Gate
Hold PGA constant (default)
Mute ADC output (digital mute)
Fade to PGA minimum value (analog fade)
Fade then mute (analog fade/digital mute)
Threshol
−76.5 dB (default)
−75 dB
−31.5 dB
−30 dB
input sig
r either a
that trigge
a −1.5 dB
Rev. 0 | Page 55 of 80
Channels per LRCLK Frame
Stereo (default)
TDM 4
TDM 8
Reserved
it data width modes.
nal falls below the threshold for 250 ms, the noise gate is activated.
d
50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK
change. See Table 71 for a complete list of the threshold settings.
gers the beginning of the left channel audio frame. This can be set
rs a change in audio data. This can be set for the falling or rising edge
Bit 3
Bit 3
L
RPOL
Bit 2
Bit 2
NGTHR[
4:0]
CHPF[1:0]
Bit 1
Bit 1
ADAU1361
Bit 0
Bit 0
MS

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