adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 53

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

R12: ALC Control 1 16402 (0x4012)
Bit 7
Table 39. ALC Control 1 Register
Bit
[7:4]
[3:0]
Bit Name
ALCHOLD[3:0]
ALCTARG[3:0]
Bit 6
ALCHOLD[3:0]
Description
ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before
increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent
distortion on low frequency signals. The hold time doubles with every 1-bit increase.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this
target level. The recommended target level is between −16 dB and −10 dB to accommodate transients witho
clipping the ADC.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit 5
Bit 4
Hold Time
2.67 ms (default
5.34 ms
10.68 m
21.3
42.72 ms
85.44 ms
170.88 ms
341.76 ms
683.52
1.367
2.734
5.4682
10.936
21.873
43.745
87.491 sec
ALC Target
−28.5 dB (default)
−27 dB
−25.5 dB
−24 dB
−22.5 d
−21 dB
−19.5 dB
−18 dB
−16.5 dB
−15 dB
−13.5 dB
−12 dB
−10.5 dB
−9 dB
−7.5 dB
−6 dB
Rev. 0 | Page 53 of 80
6 ms
1 sec
sec
ms
sec
sec
sec
sec
B
s
Bit 3
)
Bit 2
ALCTARG[3:0]
Bit 1
ADAU1361
Bit 0
ut