adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 39

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

SPI PORT
By default, the ADAU1361 is in I
SPI control mode by pulling CLATCH low three times. The SPI
port uses a 4-wire interface, consisting of CLATCH , CCLK,
CDATA, and COUT signals, and it is always a slave port. The
CLATCH signal should go low at the beginning of a transact
and high at the end of a transaction. The CCLK signal latches
CDATA on a low-to-high transition. COUT data is shifted out
of the ADAU1361 on the falling edge of CCLK and shou
clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CDATA signal carries the serial
input data, and the COUT signal is the serial output data. The
COUT signal remains three-state until a read operation is
requested. This allows other SPI-compatible peripherals to
share the same readback line. All SPI transactions have the
same basic format shown in Table 23. A timing diagram is
sh
AD
ini ted by power-cy
Chip Address R/ W
T
d
o
Tab
Byte 0
chip_adr[6:0], R/W
1
Continues to end of data.
etermines whether the communication is a read (Logic Level 1)
r a write (Logic Level 0). This format is shown in Table 22.
he LSB of the first byte of an SPI transaction is a R/ W
own in Figure 4. All data should be written MSB first. The
tia
AU1361 can be taken out of SPI mode only by a full reset
le 23. Ge
CLATCH
CDATA
neric Contro
CCLK
CLATCH
CDATA
COUT
CCLK
cling the
l Word Format
Byte 1
subaddr[15:8]
IC.
2
BYTE 0
C mode, but it can be put in
HIGH-Z
Figure 54. SPI Read from ADAU1361 Clocking (Single-Word Read Mode)
Figure 53. SPI Write to ADAU1361 Clocking (Single-Word Write Mode)
BYTE 0
BYTE 1
bit. This bit
Byte 2
subaddr[7:0]
ld be
ion
Rev. 0 | Page 39 of 80
to
BYTE 2
Table 22. ADAU1361 SPI Address and Read/ Write Byte Format
Bit 0
0
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriat
register. The MSBs of the subaddress are zero-padded to bring
the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the registe
accessed. Dur
written follow
consecutive register locations.
A sample timing diagram fo
to a register is shown in Figure 53. A sample timing diagram of
a s
COUT pin goes from being three-state to being driven at the
beginning of
the addresses and R/ W
BYTE 1
ingle-word SPI re
Bit 1
0
B
data
DATA
yte 3
Byte 3. In this example, Byte 0 to Byte 2 contain
ing a burst mode write, an initial subaddress is
ed by a continuous sequence of data for
Bit 2
0
BYTE 2
ad operatio
bit, and subsequent bytes carry the data.
Bit 3
0
r a single-word SPI write operation
n is
Bit 4
0
BYTE 3
sho
wn in Figure 5
Byte 4
data
HIGH-Z
Bit 5
0
1
ADAU1361
Bit 6
0
4. The
r being
Bit 7
R/W
e