adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 36

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
CONTROL PORTS
The ADAU1361 can operate in one of two control modes:
•
•
The ADAU1361 has both a 4-wire SPI control port and a
2-wire I
registers. The part defaults to I
SPI control mode by pulling the CLATCH pin low three times.
The control po rt is capable of full read/write operation for all
addressable registers
mode control are programmed by writing to these registers.
All addresses can be accessed in both a single-address mode or
a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
register location within the ADAU1361. This subaddress must
be two bytes long because the memory locations within the
ADAU1361 are directly addressable and their sizes exceed the
range of single-byte addressing. All subsequent bytes (starting
with Byte 3) contain the data. The number of bytes per word
depends on the type of data that is being written.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 describ
m
Table 20. Control Port Pin Functions
Pin Name
SCL/CCLK
SDA/COUT
ADDR1/CDATA
ADDR0/CLATCH
I
The ADAU1361 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1361 and the system I
In I
meaning that it cannot initiate a data transfer. Each slave device
is recognized by a unique address. The address and R/ W byte
format is shown in Table 21. The address resides in the first
seven bits of the I
ADAU1361 are set by the levels on the ADDR1 and ADDR0
pins. The LSB of the address—the R/ W bit—specifies either a
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
2
C PORT
ultiple functions.
2
C mode, the ADAU1361 is always a slave on the bus,
I
SPI control
2
C control
2
C bus control port. Both ports can be used to set the
2
C write. Bits[5:6] of the I
I
SCL: input clock
SDA: open-collector
input/output
I
I
2
2
2
C Address Bit 1: input
C Address Bit 0: input
C Mode
. Operations such as mute and input/output
2
C mode, but it can be put into
2
C master controller.
2
2
C-compatible)
C address for the
SPI Mode
COUT: output
CLATCH: input
CCLK: input clock
CDATA: input
es these
Rev. 0 | Page 36 of 80
Table 21. ADAU1361 I
Bit 0
0
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous registers. This incremen
happens automatically after a single-word write unless a stop
condition is encountered. The registers in the ADAU1361 are
one byte wide with the exception of the PLL control register,
which is six bytes wide, so the autoincrement feature kno
m
destination register. A data transfer is always terminated by a
stop condition.
The SDA and SCL pins should each have a 2 kΩ pull-up resistor
on the line connected to it. The voltage on these signal lines
should not be more than IOVDD (1.8 V to 3.3 V).
Addressing
Initially, each device on the I
monitors the SDA and SCL lines for a start condition and
the proper addr
establishing a st
o
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
R/ W
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition.
The R/ W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 47 shows the timing of an I
and Figure 48 shows an I
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, the ADAU1361 imme-
diately jumps to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADAU1361 does not issue an acknowledge and returns to the
idle condition.
n SDA while SCL remains high. This indicates that an address/
apping between subaddresses and the word length of the
bit) MSB first. The device that recognizes the transmitted
Bit 1
1
art condition, defined by a high-to-low
Bit 2
1
ess. The I C master initiates a data tra
2
Bit 3
1
C Address and Read/ Write Byte Format
2
2
C read.
2
C bus is in an idle state and
Bit 4
0
Bit 5
ADDR1
Bit 6
ADDR0
2
C write,
nsfer by
transition
ws the
Bit 7
R/W
t