adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 40

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
SERIAL D
The flexible serial data input and output ports of the ADAU1361
can be set to accept or transmit data in 2-channel format or in
a 4-channel or 8-channel TDM stream to interface to externa
ADCs or DACs. Data is processed in twos complement, MSB
first format. The left channel data field always precedes the right
channel data field in 2-channel streams. In TDM mode, Slot 0
to Slot 3 are in the first half of the audio frame, and Slot 4 to
Slot 7 are in the second half of the frame. The serial modes and
the position of the data in the frame are set in Register R15 to
Register R18 (serial port and converter control registers,
Address 0x4015 to Address 0x4018).
The serial data clocks must be synchronous with the ADAU1
master clock input. The LRCLK and BCLK pins are used to
clock both the serial input and output ports. The ADAU136
can be set as the master or the slave in a system. Because ther
is only one set of serial data clocks, the input and output ports
must always be both master or both slave.
Register R15 and Reg
Address 0x4015 and A
polarity and data input modes. The valid data formats are I
Table 25. Data Format Configurations
Format
I
Left-Justified (see
Figure 56)
R
Fi
TDM with Clock
(see Figure 58)
TDM with Pulse
(see Figure 59)
2
S (see Figure 55)
ight-Justified (see
gure 57)
LRCLK
SDATA
BCLK
LRCLK
SDATA
BCLK
ATA INPUT/OUTPUT PORTS
MSB
ister R16 (serial port control registers,
LRCLK
Frame
edge
F
edge
Frame begins on rising
edge
Frame begins on falling
edge
Frame begins on rising
edge
ddress 0x4016) allow control of clock
rame begins on rising
MSB
begins on fallin
Polarit
y (LRPOL)
LEFT CHANNEL
LEF
T CHANNEL
g
Figure 56. Left-Justified Mode—16 Bits to 24 Bits per Channel
Figure 55. I
LSB
LRCLK Mode
(LRMO
50% d
50% duty cycle
50% duty cycle
50% duty cycle
Pulse
uty cycle
LSB
2
D)
S Mode—16 Bits to 24 Bits per Channel
2
361
1
S,
Rev. 0 | Page 40 of 80
e
l
1/
f
S
BCLK Polarity
(BPOL)
Da
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
1/
f
S
ta changes
MSB
left-ju ified, r ht-just ed (24 20-/18 16-bit) nd TD . In
all m
in
do not cause a
serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1361 either as a 50% duty cycle clock
or as a bit-wide pulse.
In TDM 8 mo
48 kHz. Table 24 lists the modes in which the serial output port
can function.
Table 24. Serial Output Port Master/Slave Mode Capa
f
48 kHz
96 kHz
Table 25 describes the proper configurations for standard audi
data formats.
S
puts an arbitrary number of bits up to a limit of 24. Extra bits
odes except for the r
MSB
st
RIGHT CHANNE
2-Channel Modes (I
Justified, Right-Justified)
Master and slave
Master and slave
de, the ADAU1361 can be a master for f
ig
n error, but they are truncated internally. The
BCLK Cycles/Audio
Fram
32
32 to 64
32 to 64
64 to 256
64 to 256
to 64
RIGHT CHANNEL
e (BPF[2:0])
ifi
L
igh
t-just
LSB
-/
2
ifie
LSB
S, Left-
d mo s, the rial po
Data Delay from LRCLK
E
D
by 1 BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs
Delayed from start of word
clock by 1 BCLK
Delayed from start of word
clock by 1 BCLK
dge (LRD
elayed fr
-/
de
8-Channel TDM
Master and slave
Slave
om LRCLK edge
, a
EL[1:0])
se
S
up to
bilities
M
rt
o