mc68hc05j5ap Freescale Semiconductor, Inc, mc68hc05j5ap Datasheet - Page 61

• Manufacturer Part Number: mc68hc05j5ap
• Description: General Description The Mc68hc05j5a Is A Member Of The Low-cost High-performance M68hc05 Family Of 8-bit Microcontroller Units Mcus . The M68hc05 Family Is Based On The Customer-speci Ed Integrated Circuit Design Strategy. All Mcus In The Family
• Manufacturer: Freescale Semiconductor, Inc

9.2
REV 2.1
The timer counter registers (TCNTH, TCNTL) shown in Figure 9-3 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the timer registers has no effect. Reset of the device presets
the timer counter to $FFFC.
The TCNTL latch is a transparent read of the LSB until the a read of the TCNTH
takes place. A read of the TCNTH latches the LSB into the TCNTL location until
the TCNTL is again read. The latched value remains fixed even if multiple reads of
the TCNTH take place before the next read of the TCNTL. Therefore, when read-
ing the MSB of the timer at TCNTH the LSB of the timer at TCNTL must also be
read to complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is 16 bits and pre-
ceded by a fixed divide-by-four prescaler, the value in the counter repeats every
262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (T1OF) is set in the T1SR. When the T1OF is set, it can generate an inter-
rupt if the timer overflow interrupt enable bit (T1OIE) is also set in the T1CR. The
T1OF flag bit can only be reset by reading the TCNTL after reading the T1SR.
Other than clearing any possible T1OF flags, reading the TCNTH and TCNTL in
any order or any number of times does not have any effect on the 16-bit free-run-
ning counter.
To prevent interrupts from occurring between readings of the TCNTH and TCNTL,
set the I bit in the condition code register (CCR) before reading TCNTH and clear
the I bit after reading TCNTL.
ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer counter registers, except that any reads of the alternate
TCNTH
$0018
TCNTL
$0019
reset:
reset:
W
W
Figure 9-3. 16-Bit Timer Counter Registers (TCNTH, TCNTL)
R
R
BIT 7
Bit15
Bit7
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
BIT 6
Bit14
Bit6
1
1
Go to: www.freescale.com
BIT 5
Bit13
16-BIT TIMER
Bit5
July 16, 1999
1
1
NOTE
BIT 4
Bit12
Bit4
1
1
GENERAL RELEASE SPECIFICATION
BIT 3
Bit11
Bit3
1
1
BIT 2
Bit10
Bit2
1
1
BIT 1
Bit9
Bit1
1
0
BIT 0
Bit8
Bit0
1
0
9-3