mc68hc05j5ap Freescale Semiconductor, Inc, mc68hc05j5ap Datasheet - Page 17

• Manufacturer Part Number: mc68hc05j5ap
• Description: General Description The Mc68hc05j5a Is A Member Of The Low-cost High-performance M68hc05 Family Of 8-bit Microcontroller Units Mcus . The M68hc05 Family Is Based On The Customer-speci Ed Integrated Circuit Design Strategy. All Mcus In The Family
• Manufacturer: Freescale Semiconductor, Inc

1.5.6 PB0-PB5
REV 2.1
can be enabled or disabled by software. Both PA6 and PA7 pins have Schmitt
trigger input for better noise immunity. V
respectively.
The slow transition feature of PA6 and PA7 pins can be enabled or disabled by
software. Once enabled, slow transition feature is applied to both pins while in
output mode.
I/O lines PB2 to PB5 are not available on the 16-pin package.
These six I/O lines comprise Port B. PB0, PB3 to PB5 are push-pull I/O lines with
pull-down resistor. PB1 and PB2 are open-drain I/O lines with pull-up resistor.
The state of any line is software programmable and is configured as an input
during power-on or reset. I/O lines PB1 and PB2 have software programmable
pull-up device, whereas PB0, PB3 to PB5 have software programmable pull-down
device, provided by mask option. Pull-up devices on PB1 and PB2 lines once
enabled are always enabled regardless of pin direction configuration; unlike pull-
down devices on PB0, PB3-PB5 lines, which are activated only when the pin is
configured as input pin.
Similar to PA6 and PA7, PB1 also has a slow output falling transition feature when
configured as an output line. PB1 has 25mA sink capability at 0.5V V
PB2 output is one clock cycle (250ns if bus rate is 2MHz) late than other I/O pins
if slow output transition feature is enabled. PB2 has 25mA sink capability at 0.5V
V
For the 16-pin package, PB1 and PB2 are bonded to the same pin and is labelled
PB1. This PB1 pin has 50mA sink capability if PB1 and PB2 data register bits they
are written with the same value at the same write cycle. The falling transition time
of PB1 is set at 250ns typical at a specified load of 50pF, assuming that the bus
rate is 2MHz. The slow transition feature on this PB1 pin is longer than PB1 pin for
the 20-pin package.
If Port Data Register PB1 and PB2 are not written with the same value, PB1 pin
on the 16-pin package will sink 25mA only and the output transition time will be
shorter.
OL
.
Freescale Semiconductor, Inc.
For More Information On This Product,
GENERAL DESCRIPTION
Go to: www.freescale.com
July 16, 1999
NOTE
NOTE
NOTE
IH
and V
IL
GENERAL RELEASE SPECIFICATION
are specified at 2.4V and 0.8V,
OL
.
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