mc68hc05j5ap Freescale Semiconductor, Inc, mc68hc05j5ap Datasheet - Page 46

• Manufacturer Part Number: mc68hc05j5ap
• Description: General Description The Mc68hc05j5a Is A Member Of The Low-cost High-performance M68hc05 Family Of 8-bit Microcontroller Units Mcus . The M68hc05 Family Is Based On The Customer-speci Ed Integrated Circuit Design Strategy. All Mcus In The Family
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
7.2.1 Port A Data Register
7.2.2 Port A Data Direction Register
7-2
Note1: All the I/O port pins may have either pullup or pulldown device.
Note2: PA6 and PA7 output drivers are the open-drained type
Internal HC05
Data Bus
Read $0004
Read $0000
Write $0004
Write $0000
Write $0010
Each Port A pin is controlled by the corresponding bits in a data direction register,
a data register and a pulldown/up register. The Port A Data Register is located at
address $0000. The Port A Data Direction Register (DDRA) is located at address
$0004. The Port A Pulldown/up Register (PDURA) is located at address $0010.
Reset operation will clear the DDRA and the PDURA. The Port A Data Register is
unaffected by reset.
Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a
Port A pin is programmed as output, the corresponding data register bit deter-
mines the logic state of that pin. When a Port A pin is programmed as input, any
read from the Port A Data Register will return the logic state of the corresponding
I/O pin. The Port A data register is unaffected by reset.
Each Port A I/O pin may be programmed as input by clearing the corresponding
bit in the DDRA, or programmed as output by setting the corresponding bit in the
DDRA. The DDRA can be accessed at address $0004. The DDRA is cleared by
reset.
If configured as output pins, PA6 and PA7 have slow output falling-edge transition
feature. The slow transition feature is controlled by the SLOWE bit of DDRB.
SLOWE bit, if set and if the pin is configured as an output pin, enables the slow
falling-edge output transition feature of all four I/O lines, PA6, PA7, PB1, and PB2.
(RST)
Reset
Freescale Semiconductor, Inc.
For More Information On This Product,
(Software Pulldown/up Inhibit)
Figure 7-2. Port A I/O Circuitry
Data Direction
Pulldown/up
Register Bit
Register Bit
Register Bit
Data
Go to: www.freescale.com
INPUT/OUTPUT PORTS
July 16, 1999
Mask Option
Output
100 A
Pulldown
PA0-PA3 and PA7 only:
interrupt system
to IRQ
MC68HC05J5A
VDD
8 mA Sink
Capability
(Bits 4-7 Only)
5K
Pullup
REV 2.1
I/O
Pin