mc68hc05j5ap Freescale Semiconductor, Inc, mc68hc05j5ap Datasheet - Page 29

• Manufacturer Part Number: mc68hc05j5ap
• Description: General Description The Mc68hc05j5a Is A Member Of The Low-cost High-performance M68hc05 Family Of 8-bit Microcontroller Units Mcus . The M68hc05 Family Is Based On The Customer-speci Ed Integrated Circuit Design Strategy. All Mcus In The Family
• Manufacturer: Freescale Semiconductor, Inc

4.3
4.4
4.5
REV 2.1
(Port A External Int.)
IRQ Fetch Vector
Mask Option
Mask Option
(IRQ Level)
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the con-
tents of memory locations $0FFC and $0FFD.
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
EXTERNAL INTERRUPT (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in Figure 4-2.
IRQ Pin
IRQE1
IRQE1
IRQR1
IRQE
IRQR
PA0
PA1
PA2
PA3
PA7
RST
RST
Figure 4-2. IRQ Function Block Diagram
Freescale Semiconductor, Inc.
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INTERRUPTS
July 16, 1999
V
DD
V
DD
LATCH
IRQ1
LATCH
GENERAL RELEASE SPECIFICATION
IRQ
R
R
IRQF1
to BIH & BIL
instruction
sensing
to IRQ
processing
in CPU
IRQF
4-3