ep1s25 Altera Corporation, ep1s25 Datasheet - Page 96

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

PLLs & Clock Networks
2–82
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–18. Stratix Device PLL Availability
Device
PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
PLLs 11 and 12 each have one single-ended output.
EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA
Table
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v
v
v
v
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2–18:
1
v
v
v
v
v
v
v
2
provide general purpose clocking with multiplication and phase shifting
as well as high-speed outputs for high-speed differential I/O support.
Enhanced and fast PLLs work together with the Stratix high-speed I/O
and advanced clock architecture to provide significant improvements in
system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices.
each Stratix device.
v
v
v
v
v
v
v
3
v
v
v
v
v
v
v
4
Fast PLLs
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v
v
v
7
(3)
(3)
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v
v
v
8
(3)
(3)
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v
v
Table 2–18
9
(3)
(3)
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v
v
v
10
(3)
(3)
shows the PLLs available for
5(1)
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v
®
package.
Enhanced PLLs
6(1)
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v
Altera Corporation
v(3) v(3)
11(2) 12(2)
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v
July 2005
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v