ep1s25 Altera Corporation, ep1s25 Datasheet - Page 258

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

f
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
f
W
f
operation
(LVDS,
LVPECL,
HyperTransport
technology)
HSCLK
HSCLK
HSDR
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 4)
Symbol
Device
(Clock
= f
HSDR
/
W = 4 to 30
(Serdes used)
W = 2 (Serdes
bypass)
W = 2 (Serdes
used)
W = 1 (Serdes
bypass)
W = 1 (Serdes
used)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1 (LVDS
and LVPECL
only)
Conditions
Tables 4–125
Min
150
100
300
300
300
300
300
100
100
10
50
-5 Speed Grade
and
Typ
4–126
Max
210
231
420
462
717
840
840
840
840
462
462
show the high-speed I/O timing for Stratix devices.
Min
150
100
300
300
300
300
300
100
100
10
50
-6 Speed Grade
Typ
Max
210
231
420
462
717
840
840
840
840
462
462
Notes
Min
150
100
300
300
300
300
300
100
100
10
50
(1),
-7 Speed Grade
(2)
Typ
Max
156
231
312
462
624
640
640
640
640
640
640
Min
150
100
300
300
300
300
300
100
100
10
50
-8 Speed Grade
Typ
115.5
Max
231
231
462
462
462
462
462
462
462
462
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
Unit