ep1s25 Altera Corporation, ep1s25 Datasheet - Page 81

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–37. Multiply-Accumulate Mode
Notes to
(1)
(2)
Altera Corporation
July 2005
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Shiftout B Shiftout A
Figure
Shiftin B
2–37:
ENA
ENA
D
D
CLRN
CLRN
Shiftin A
Q
Q
signa (1)
signb (1)
clock
Multiply-Accumulator Mode
In multiply-accumulator mode (see
multiplied results to the adder/subtractor/accumulator block configured
as an accumulator. You can implement one or two multiply-accumulators
up to 18 × 18 bits in one DSP block. The first and third multiplier sub-
blocks are unused in this mode, because only one multiplier can feed one
of two accumulators. The multiply-accumulator output can be up to 52
bits—a maximum of a 36-bit result with 16 bits of accumulation. The
accum_sload and overflow signals are only available in this mode.
The addnsub signal can set the accumulator for decimation and the
overflow signal indicates underflow condition.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator
block to add or subtract the outputs of the multiplier block, which is
useful for applications such as FFT functions and complex FIR filters. A
ena
aclr
ENA
D
CLRN
Q
accum_sload (2)
addnsub (2)
signa (2)
signb (2)
Figure
Accumulator
Stratix Device Handbook, Volume 1
2–37), the DSP block drives
ENA
D
CLRN
Stratix Architecture
Q
Data Out
overflow
2–67