ep1s25 Altera Corporation, ep1s25 Datasheet - Page 47

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–17. M4K RAM Block Control Signals
Figure 2–18. M4K RAM Block LAB Row Interface
Altera Corporation
July 2005
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 and C8
Interconnects
8
clock_a
M4K RAM Block Local
Interconnect Region
10
clocken_a
renwe_a
Byte enable
Clocks
address
LAB Row Clocks
alcr_a
M4K RAM
Block
datain
alcr_b
dataout
Signals
Control
renwe_b
clocken_b
Stratix Device Handbook, Volume 1
8
clock_b
Stratix Architecture
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 and R8
Interconnects
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
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