dsp56852 Freescale Semiconductor, Inc, dsp56852 Datasheet - Page 36

• Manufacturer Part Number: dsp56852
• Description: 56800e 16-bit Digital Signal Controllers Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

36
Operating Conditions: V
SRFS (wl) input
STFS (wl) input
SRFS (bl) input
SRXD Hold time after SRCK low - Slave
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slave
SRXD Hold time after STCK low - Slave
STFS (bl) input
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length
SRCK input
STCK input
SRXD
STXD
Table 4-12 SSI Slave Mode
SS
= V
t
SSIO
FTXES
t
t
TXES
SCKH
t
Parameter
t
t
RFSWHS
TXVS
RFSBHS
= V
t
t
TFSWHS
SS
t
SSA
TFSBHS
t
Figure 4-23 Slave Mode Clock Timing
SCKW
= 0V, V
t
FTXVS
t
SCKL
DD
First Bit
t
56852 Technical Data, Rev. 8
= 1.62-1.98V, V
HS
1
t
Switching Characteristics (Continued)
TFSBLS
t
t
RFSBLS
TXNVS
t
TSS
DDIO
= V
DDA
t
THS
= 3.0–3.6V, T
Symbol
t
t
t
TSS
THS
HS
A
= –40° to +120°C, C
Min
4
4
4
Last Bit
Typ
Freescale Semiconductor
L
≤ 50pF, f
Max
—
—
—
t
t
TFSWLS
RFSWLS
t
TXHIS
op
= 120MHz
Units
ns
?
?