dsp56852 Freescale Semiconductor, Inc, dsp56852 Datasheet - Page 11

• Manufacturer Part Number: dsp56852
• Description: 56800e 16-bit Digital Signal Controllers Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No.
D3
C3
G7
H7
H8
G8
H9
G6
D8
D7
D9
C8
F8
F7
E8
E7
E6
A9
E2
Signal Name
MODE A
MODE B
MODE C
GPIOA1
GPIOA2
CS1
CS2
D10
D11
D12
D13
D14
D15
RD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Input/Output
Input/Output
Input/Output
Input/Output
Output
Output
Output
Type
56852 Technical Data, Rev. 8
external memory accesses that fall within a programmable address
range.
external memory accesses that fall within a programmable address
range.
Port A GPIO (2) —A general purpose IO pin.
Data Bus (D0–D12) —specify the data for external program or data
memory accesses. D0–D15 are tri-stated when the external bus is inactive.
Data Bus (D13–D15) — specify the data for external program or data
memory accesses. D0–D15 are tri-stated when the external bus is inactive.
Mode Select—During the bootstrap process the MODE A, MODE B,
and MODE C pins select one of the eight bootstrap modes. These pins
are sampled at the end of reset.
Note: Any time POR and EXTERNAL resets are active, the state of
MODE A, B and C pins get asynchronously transferred to the SIM
Control Register [14:12] ($1FFF08) respectively. These bits determine
the mode in which the part will boot up.
Note: Software and COP resets do not update the SIM Control
Register.
Bus Control– Read Enable (RD)—is asserted during external memory
read cycles. When RD is asserted low, pins D0–D15 become inputs
and an external device is enabled onto the data bus. When RD is
deasserted high, the external data is latched inside the controller. RD
can be connected directly to the OE pin of a Static RAM or ROM.
Chip Select 1 (CS1) —When enabled, a CSx signal is asserted for
Port A GPIO (1) —A general purpose IO pin.
Chip Select 2 (CS2)—When enabled, a CSx signal is asserted for
Description
Introduction
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