dsp56852 Freescale Semiconductor, Inc, dsp56852 Datasheet - Page 23

• Manufacturer Part Number: dsp56852
• Description: 56800e 16-bit Digital Signal Controllers Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices.
shows sample timing and parameters that are detailed in
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as
user controlled wait states. The equation:
Freescale Semiconductor
Operating Conditions: V
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
t
D fixed portion of the delay, due to on-chip path delays.
P
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
W the sum of the applicable wait state controls. See the “Wait State Controls” column of
External
Note: The midpoint is V
Clock
parameter delay time
the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
clock duty cycle derating.
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
t = D + P * (M + W)
Characteristic
SS
10%
= V
50%
90%
2
SSIO
t
PW
= V
IL
+ (V
SSA
= 0V, V
Figure 4-9 External Clock Timing
IH
– V
IL
DD
)/2.
Table 4-6 PLL Timing
56852 Technical Data, Rev. 8
= 1.62-1.98V, V
t
PW
1
Symbol
DDIO
f
t
f
osc
plls
clk
= V
Table
DDA
= 3.0–3.6V, T
Min
4-7.
40
—
2
t
fall
A
= –40° to +120°C, C
Typ
—
4
1
External Memory Interface Timing
t
Max
rise
240
10
L
4
£ 50pF, f
10%
50%
90%
op
Table 4-7
Figure 4-10
V
V
= 120MHz
Unit
MHz
MHz
IH
IL
ms
for
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