adsp-bf561wbbz-5a Analog Devices, Inc., adsp-bf561wbbz-5a Datasheet - Page 13

• Manufacturer Part Number: adsp-bf561wbbz-5a
• Description: Blackfin Embedded Symmetric Multi-processor
• Manufacturer: Analog Devices, Inc.

For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site
log.com)—use site search on “EE-228”.
CLOCK SIGNALS
The ADSP-BF561 processor can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 processor includes an
on-chip oscillator circuit, an external crystal may be used. For
fundamental frequency operation, use the circuit shown in
Figure
processor-grade crystal is connected across the CLKIN and
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 k: range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in
the sine frequency. The capacitor and resistor values shown in
Figure 5
dent upon the crystal manufacturer’s load capacitance
recommendations and the physical PCB layout. The resistor
value depends on the drive level specified by the crystal manu-
facturer. System designs should verify the customized values
based on careful investigation on multiple devices over the
allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
CLKOUT
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
5. A parallel-resonant, fundamental frequency, micro-
are typical values only. The capacitor values are depen-
Figure
Figure 5. External Crystal Connections
5.
Figure 5
EN
CLKIN
18pF*
Blackfin
fine tune the phase and amplitude of
TO PLL CIRCUITRY
XTAL
18pF*
FOR OVERTONE
OPERATION ONLY:
(www.ana-
Rev. C | Page 13 of 64 | December 2007
As shown in
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user-programmable 0.5u to 64u multiplica-
tion factor. The default multiplier is 10u, but it can be modified
by a software instruction sequence. On the fly frequency
changes can be effected by simply writing to the PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 5. Example System Clock Ratios
The maximum frequency of the system clock is f
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Signal Name
SSEL3–0
0001
0110
1010
Table 5
CLKIN
illustrates typical system clock ratios.
Figure
Figure 6. Frequency Modification Methods
REQUIRES PLL SEQUENCING
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
“FINE” ADJUSTMENT
0.5u TO 64u
6, the core clock (CCLK) and system
PLL
SCLK
. The SSEL value can be changed
SCLK d 133MHz
VCO
SCLK d CCLK
Example Frequency
Ratios (MHz)
VCO
100
300
500
“COARSE” ADJUSTMENT
ADSP-BF561
÷ 1, 2, 4, 8
÷ 1 TO 15
ON-THE-FLY
SCLK
SCLK
100
50
50
. Note that
CCLK
SCLK