adsp-bf561wbbz-5a Analog Devices, Inc., adsp-bf561wbbz-5a Datasheet
adsp-bf561wbbz-5a
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adsp-bf561wbbz-5a Summary of contents
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... CORE SYSTEM/BUS INTERFACE DMA DAB PAB PPI0 PPI1 Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 2 S channels UART IrDA SPI L1 L2 SRAM 128K BYTES SPORT0 SPORT1 IMDMA CONTROLLER ...
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... ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 3 Portable Low Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Watchdog Timer .................................................. 8 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ......................... 9 UART Port .......................................................... 9 Programmable Flags (PFx) .................................... 10 Parallel Peripheral Interface ................................... 10 Dynamic Power Management ................................ 11 Voltage Regulation .............................................. 12 Voltage Regulator Layout Guidelines .................... 12 Clock Signals ...
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... GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of ® the Blackfin family of products targeting a variety of multime- dia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Black- fin processors. These Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantage of a ...
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... R1.L R0.H R0.L MEMORY ARCHITECTURE The ADSP-BF561 views memory as a single unified 4G byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierar- ...
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... Mapped Registers (MMRs) but share the same system MMR registers and 128K bytes L2 SRAM memory. External (Off-Chip) Memory The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection four banks of synchronous DRAM CORE A MEMORY MAP ...
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... The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writ- ing the appropriate values into the Interrupt Assignment Registers (SIC_IAR7– ...
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... Supplemental Interrupt 1 IVG8 IVG9 Event Control IVG9 The ADSP-BF561 provides the user with a very flexible mecha- IVG9 nism to control the processing of events. In the CEC, three IVG9 registers are used to coordinate and control events. Each of the registers is 16 bits wide, while each bit represents a particular IVG9 event class ...
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... DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories. WATCHDOG TIMER Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the proces- sor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software ...
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... The timer is clocked by the system clock (SCLK maximum frequency SCLK TIMERS There are 14 programmable timer units in the ADSP-BF561. Each of the 12 general-purpose timer units can be indepen- dently programmed as a Pulse Width Modulator (PWM), internally or externally clocked timer, or pulse width counter. The general-purpose timer units can be used in conjunction ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF561 processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Rev Page December 2007 ...
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... In addition, dynamic power management provides the control functions to dynamically alter the proces- sor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF561 peripherals also reduces power consumption. See Table 3 power settings for each mode. ...
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... The use of multiple power domains maximizes flexibility, while maintaining compliance with industry stan- dards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, the processor can take advantage of Dynamic Power Manage- ment, without affecting the I/O devices. There are no sequencing requirements for the various power domains ...
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... Analog Devices web site log.com)—use site search on “EE-228”. CLOCK SIGNALS The ADSP-BF561 processor can be clocked by an external crys- tal, a sine wave input buffered, shaped clock derived from an external clock oscillator external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation ...
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... The time base for the PLL_LOCKCNT register is the period of CLKIN. BOOTING MODES The ADSP-BF561 has three mechanisms (listed in automatically loading internal L1 instruction memory, L2, or external memory after a reset. A fourth mode is provided to exe- cute from external memory, bypassing the boot sequence. ...
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... Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides full- speed emulation, allowing inspection and modification of mem- ory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’ ...
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... Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on the ADSP-BF561. The emulator uses the TAP to access the internal features of the processor, allow- ing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers ...
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... PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in maintain maximum function and reduce package size and pin count, some pins have multiple functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. All pins are three-stated during and immediately after reset, except the external memory interface, asynchronous memory control, and synchronous memory control pins ...
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... ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name Type Function PF/SPI/TIMER PF0/SPISS/TMR0 I/O Programmable Flag/Slave SPI Select/Timer PF1/SPISEL1/TMR1 I/O Programmable Flag/SPI Select/Timer PF2/SPISEL2/TMR2 I/O Programmable Flag/SPI Select/Timer PF3/SPISEL3/TMR3 I/O Programmable Flag/SPI Select/Timer PF4/SPISEL4/TMR4 I/O Programmable Flag/SPI Select/Timer PF5/SPISEL5/TMR5 I/O Programmable Flag/SPI Select/Timer PF6/SPISEL6/TMR6 I/O Programmable Flag/SPI Select/Timer PF7/SPISEL7/TMR7 I/O Programmable Flag/SPI Select/Timer ...
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... VROUT1–0 O External FET Drive Supplies VDDEXT P Power Supply VDDINT P Power Supply GND G Power Supply Return No Connection Refer to Figure 28 on Page 41 to Figure 32 on Page 42. Rev Page December 2007 ADSP-BF561 Driver 1 Type ...
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... Applies to all signal pins. 7 Guaranteed, but not tested. 8 Maximum current drawn. See Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)—use site search on “EE-293”. 9 Both cores executing 75% dual MAC, 25% ADD instructions with moderate data bus activity. 2 ...
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... Rev Page December 2007 ADSP-BF561 Figure 7 and Table 10 provides Ordering 64. a ADSP-BF561 tppZccc vvvvvv.x n.n yyww country_of_origin B Figure 7. Product Information on Package Field Description Temperature Range Package Type RoHS Compliant Part See Ordering Guide Assembly Lot Code Silicon Revision ...
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... ADSP-BF561 TIMING SPECIFICATIONS Table 11 through Table 12 describe the timing requirements for the ADSP-BF561 clocks (t = 1/f CCLK CCLK MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock, and Voltage Controlled Oscillator Table 11. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models ...
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... CLKIN (not including startup time of external clock oscillator). t CKIN CLKIN t CKINL RESET 4 maximum period and the t CLKIN t CKINH t WRST Figure 8. Clock and Reset Timing Rev Page December 2007 ADSP-BF561 Min Max 25.0 100.0 10.0 10 CKIN minimum period is 12.5 ns. CLKIN , f , and f settings discussed in Table 11 on Page 22 VCO ...
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... ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 16. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA31–0 Setup Before CLKOUT SDAT t DATA31–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics t Output Delay After CLKOUT ...
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... ARDY t END AT DATA15–0 WRITE DATA 1 1 ACCESS PROGRAMMED WRITE HOLD EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE HARDY SARDY t SARDY Figure 10. Asynchronous Memory Write Cycle Timing Rev Page December 2007 ADSP-BF561 Min Max 4.0 0.0 6.0 1.0 6.0 0 Unit ...
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... ADSP-BF561 SDRAM Interface Timing Table 18. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before CLKOUT SSDAT t DATA Hold After CLKOUT HSDAT Switching Characteristics 1 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL t Command, ADDR, Data Delay After CLKOUT ...
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... The pad loads for these timing parameters are 20 pF. CLKOUT AMSx ADDR25-2 ABE3-0 AWE ARE BG BGH Figure 12. External Port Bus Request and Grant Cycle Timing Rev Page December 2007 ADSP-BF561 Min Max 4.6 0.0 4.5 4.5 3.6 3.6 3.6 3 DBG t EBG t ...
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... ADSP-BF561 Parallel Peripheral Interface Timing Table 20, and Figure 13 through Figure 16 on Page default Parallel Peripheral Interface operations. Table 20. Parallel Peripheral Interface Timing Parameter Timing Requirements 1 t PPIxCLK Width PCLKW 1 t PPIxCLK Period PCLK t External Frame Sync Setup Before PPIxCLK SFSPE t External Frame Sync Hold After PPIxCLK ...
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... DFSPE t HOFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 PPIx_DATA Figure 15. PPI GP Tx Mode with Internal Frame Sync Timing (Default) FRAME SYNC IS SAMPLED FOR DATA1 IS DATA0 SAMPLED t HFSPE t SFSPE t HDRPE DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Rev Page December 2007 ADSP-BF561 ...
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... ADSP-BF561 PPIxCLK POLC = 0 PPIxCLK POLC = 1 POLS = 1 PPxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 PPIx_DATA PPIxCLK POLC = 0 PPIxCLK POLC = 1 t SFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 PPIx_DATA Figure 17. PPI GP Rx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set) FRAME DATA0 IS SYNC IS ...
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... PPIxCLK POLC = 0 PPIxCLK POLC = 1 t SFSPE POLS = 1 PPIxSYNC1 POLS = 0 POLS = 1 PPIxSYNC2 POLS = 0 PPIx_DATA Figure 18. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set) DATA DRIVING/ FRAME SYNC SAMPLING EDGE t HFSPE t DDTPE t HDTPE Rev Page December 2007 ADSP-BF561 ...
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... ADSP-BF561 Serial Ports Table 21 through Table 24 on Page 34 and through Figure 20 on Page 34 describe Serial Port operations. Table 21. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx HFSE t Receive Data Setup Before RSCLKx SDRE ...
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... HFSI HOFSE RFSx t HDRI DRx DATA TRANSMIT—EXTERNAL CLOCK EDGE TSCLKx t t HFSI HOFSE TFSx t HDTE DTx Figure 19. Serial Ports Rev Page December 2007 ADSP-BF561 DRIVE SAMPLE EDGE EDGE t SCLKEW t DFSE t SFSE t SDRE DRIVE SAMPLE EDGE EDGE t SCLKEW t DFSE ...
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... ADSP-BF561 Table 23. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable Delay from External TSCLKx DTENE t Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. ...
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... SPICHM t t DDSPIDM HDSPIDM MSB t t HSPIDM SSPIDM MSB VALID t DDSPIDM MSB t HSPIDM LSB VALID Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing Rev Page December 2007 ADSP-BF561 Min Max 7.5 –1.5 2t – 1.5 SCLK 2t – 0.5 SCLK 2t – 1.5 SCLK 4t – 1.5 SCLK 2t – 1.5 ...
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... ADSP-BF561 Serial Peripheral Interface (SPI) Port— Slave Timing Table 26 and Figure 22 describe SPI port slave operations. Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period ...
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... UART TRANSMIT INTERRUPT Figure 23, DATA8–5 START DATA8–5 Figure 23. UART Port—Receive and Transmit Timing Rev Page December 2007 ADSP-BF561 STOP UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ STOP2–1 UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT ...
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... ADSP-BF561 Programmable Flags Cycle Timing Table 27 and Figure 24 describe programmable flag operations. Table 27. Programmable Flags Cycle Timing Parameter Timing Requirement t Flag Input Pulse Width WFI Switching Characteristic t Flag Output Delay from CLKOUT Low DFO CLKOUT PFx (OUTPUT) PFx (INPUT) t DFO FLAG OUTPUT ...
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... HTO CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) 32 equals (2 –1) cycles. HTO t HTO Figure 25. Timer PWM_OUT Cycle Timing Rev Page December 2007 ADSP-BF561 Min Max Unit 1 SCLK 1 SCLK –1) SCLK ...
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... ADSP-BF561 JTAG Test and Emulation Port Timing Table 29 and Figure 26 describe JTAG port operations. Table 29. JTAG Port Timing Parameter Timing Parameters t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 27 through Figure 34 on Page 42 voltage characteristics for the output drivers of the ADSP-BF561 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Refer to Table 8 on Page 17 to identify the driver type for a pin. ...
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... POWER DISSIPATION Many operating conditions can affect power dissipation. System V = 3.65V DDEXT V = 3.30V designers should refer to Estimating Power for ADSP-BF561 DDEXT V = 2.95V DDEXT Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)—use site search on “EE-293.” This docu- ment provides detailed information for optimizing your design for lowest power ...
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... To determine the data output hold time in a particular system, using the equation given above. Choose 'V first calculate t DECAY to be the difference between the ADSP-BF561 processor’s out- put voltage and the input threshold for the device requiring the hold time the total bus capacitance (per data line), and I L the total leakage or three-state current (per data line) ...
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... ADSP-BF561 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver (max) DDEXT 30 25 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance ...
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... Linear m/s Airflow JMA T 2 Linear m/s Airflow JMA T Not Applicable JB T Not Applicable JC < 0 Linear m/s Airflow JT < 1 Linear m/s Airflow JT < 2 Linear m/s Airflow JT Table 32 is the figure represents the JT are provided for JB Typical Unit 18.1 C/W 15.9 C/W 15.1 C/W 3.72 C/W 0.11 C/W 0.18 C/W 0.18 C/W Typical Unit 25.6 C/W 22.4 C/W 21.6 C/W 18.9 C/W 4.85 C/W 0.15 C/W n/a C/W n/a C/W Typical Unit 20.6 C/W 17.8 C/W 17.4 C/W 16.3 C/W 7.15 C/W 0.37 C/W n/a C/W n/a C/W Rev Page December 2007 ADSP-BF561 ...
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... ADSP-BF561 256-BALL CSP_BGA (17 mm) BALL ASSIGNMENT Table 33 lists the 256-Ball CSP_BGA (17 mm × 17 mm) ball assignment by ball number. Table 34 on Page 48 assignment alphabetically by signal. Table 33. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A1 VDDEXT C9 A2 ...
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... R7 PF11 T3 SCK R8 PF14 T4 RFS1 R9 TCK T5 TFS1 R10 TRST T6 DR0SEC R11 SLEEP T7 DT0SEC R12 MOSI T8 Rev Page December 2007 ADSP-BF561 Signal Ball No. Signal RSCLK1 T9 TDO TSCLK1 T10 TDI NC T11 EMU TFS0 T12 MISO VDDEXT T13 TX NC T14 DR1PRI PPI1D3 T15 DT1PRI ...
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... ADSP-BF561 Table 34. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal ABE0 C12 BR ABE1 D12 BYPASS ABE2 A12 CLKIN ABE3 A13 DATA0 ADDR02 B15 DATA01 ADDR03 A15 DATA02 ADDR04 C14 DATA03 ADDR05 B14 DATA04 ADDR06 A14 DATA05 ADDR07 ...
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... K5 F5 VDDEXT K6 F6 VDDEXT K11 F7 VDDEXT L5 F10 VDDEXT L6 F11 VDDEXT L7 F12 VDDEXT L8 G2 VDDEXT L10 Rev Page December 2007 ADSP-BF561 Signal Ball No. Signal VDDEXT L11 VDDINT VDDEXT L12 VDDINT VDDEXT T1 VDDINT VDDEXT T16 VDDINT VDDINT E6 VDDINT VDDINT E8 VROUT0 VDDINT E10 ...
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... ADSP-BF561 Figure 46 lists the top view of the 256-Ball CSP_BGA (17 mm × 17 mm) ball configuration. Figure 47 view. A1 BALL PAD CORNER TOP VIEW ...
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... H03 PPI0D9 DATA2 H04 PPI0D7 GND H05 PPI0D5 DATA4 H06 VDDINT DATA7 H07 VDDINT VDDEXT H08 GND Rev Page December 2007 ADSP-BF561 Ball No. Signal Ball No. H09 GND L01 H10 GND L02 H11 VDDINT L03 H12 DATA16 L04 H13 DATA18 L05 ...
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... ADSP-BF561 Table 35. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. N09 TDO P05 N10 BMODE1 P06 N11 MOSI P07 N12 GND P08 N13 RFS1 P09 N14 GND P10 N15 DT0SEC P11 N16 TSCLK0 P12 P01 ...
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... GND L16 GND J12 GND M15 GND L12 GND P16 GND M12 GND T14 GND M16 GND Rev Page December 2007 ADSP-BF561 Ball No. Signal Ball No. N15 GND N14 R15 GND P02 T15 GND P05 R11 GND P09 C05 GND P12 ...
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... ADSP-BF561 Table 36. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal PPI0D12 E03 PPI1SYNC1 PPI0D13 D01 PPI1SYNC2 PPI0D14 G05 PPI1SYNC3 PPI0D15 D02 RESET PPI0SYNC1 E04 RFS0 PPI0SYNC2 C01 RFS1 PPI0SYNC3 D03 RSCLK0 PPI1CLK B01 RSCLK1 PPI1D0 R04 ...
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... V DDEXT Figure 48. 256-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER KEY Figure 49. 256-Ball CSP_BGA Ball Configuration (Bottom View) Rev Page December 2007 ADSP-BF561 GND NC I/O V ROUT V DDINT GND NC V DDEXT I/O V ROUT ...
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... ADSP-BF561 297-BALL PBGA BALL ASSIGNMENT Table 37 lists the 297-Ball PBGA ball assignment numerically by ball number. Table 38 on Page 58 lists the ball assignment alphabetically by signal. Table 37. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A01 GND B15 A02 ADDR25 B16 ...
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... GND AE15 TRST TFS0 AE16 EMU DR0PRI AE17 BMODE1 PPI1D9 AE18 BMODE0 PPI1D8 AE19 MISO GND AE20 MOSI Rev Page December 2007 ADSP-BF561 Ball No. Signal AE21 RX AE22 RFS1 AE23 DR1SEC AE24 TFS1 AE25 GND AE26 NC AF01 GND AF02 PPI1D4 AF03 ...
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... ADSP-BF561 Table 38. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal ABE0 A22 BR ABE1 B22 BYPASS ABE2 A23 CLKIN ABE3 B23 DATA0 ADDR02 D25 DATA1 ADDR03 C26 DATA2 ADDR04 C25 DATA3 ADDR05 B26 DATA4 ADDR06 A25 DATA5 ADDR07 B24 DATA6 ADDR08 ...
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... VDDEXT Y02 VDDEXT Y01 VDDEXT W01 VDDEXT W02 VDDEXT V01 VDDEXT H02 VDDEXT AC26 VDDEXT AE22 VDDEXT Rev Page December 2007 ADSP-BF561 Ball No. Signal Ball No. AD26 VDDEXT K13 AF21 VDDEXT K14 AE21 VDDEXT K15 B19 VDDEXT L10 A18 VDDEXT M10 ...
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... ADSP-BF561 Figure 50 lists the top view of the 297-Ball PBGA ball configura- tion. Figure 51 lists the bottom view TOP VIEW ...
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... CSP_BGA (BC-256-4) 15.00 BSC SQ 1.00 BSC CL BALL PITCH BOTTOM VIEW DETAIL A 0.20 MAX COPLANARITY 0.70 DETAIL A BALL DIAMETER 0.60 0.50 Rev Page December 2007 ADSP-BF561 A1 BALL PAD CORNER 0.45 MIN SEATING PLANE ...
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... ADSP-BF561 12.00 BSC SQ A1 BALL PAD CORNER TOP VIEW 1.70 1.51 1.36 SIDE VIEW NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.25 Figure 53. 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-1) 9 ...
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... BALL DIAMETER 0.60 0.50 Figure 54. 297-Ball Plastic Ball Grid Array (PBGA) (B-297) Ball Attach Type Solder Mask Opening Solder Mask Defined 0.30 mm diameter Solder Mask Defined 0.43 mm diameter Solder Mask Defined 0.43 mm diameter Rev Page December 2007 ADSP-BF561 25.00 BSC SQ A1 BALL 8.00 PAD CORNER CL 8. ...
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... MHz ADSP-BF561SBB500 –40°C to +85°C 500 MHz 2 ADSP-BF561SBBZ600 –40°C to +85°C 600 MHz 2 ADSP-BF561SBBZ500 –40°C to +85°C 500 MHz 2, 3 ADSP-BF561WBBZ-5A –40°C to +85°C 533 MHz 2 ADSP-BF561SKBCZ-6A 0°C to +70°C 2 ADSP-BF561SKBCZ-5A 0°C to +70°C 2 ADSP-BF561SBBCZ-6A – ...