adsp-bf561wbbz-5a Analog Devices, Inc., adsp-bf561wbbz-5a Datasheet - Page 10

• Manufacturer Part Number: adsp-bf561wbbz-5a
• Description: Blackfin Embedded Symmetric Multi-processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF561
The baud rate, serial data format, error code generation and
status, and interrupts for the UART port are programmable.
The UART programmable features include:
The UART port’s clock rate is calculated as:
Where the 16-bit UART_Divisor comes from the UART_DLH
register (most significant 8 bits) and UART_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA
cal layer link specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFx)
The ADSP-BF561 has 48 bidirectional, general-purpose I/O,
programmable flag (PF47–0) pins. Some programmable flag
pins are used by peripherals (see
When not used as a peripheral pin, each programmable flag can
be individually controlled by manipulation of the flag control,
status, and interrupt registers as follows:
• Supporting bit rates ranging from (f
• Supporting data formats from seven bits to 12 bits per
• Both transmit and receive operations can be configured to
• Flag direction control register – Specifies the direction of
• Flag control and status registers – Rather than forcing the
• Flag interrupt mask registers – These registers allow each
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
second to (f
frame.
generate maskable interrupts to the processor.
each individual PFx pin as input or output.
software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a
“write one to set” and “write one to clear” mechanism that
allows any combination of individual flags to be set or
cleared in a single instruction, without affecting the level of
any other flags. Two control registers are provided, one
register is written-to in order to set flag values, while
another register is written-to in order to clear flag values.
Reading the flag status register allows software to interro-
gate the sense of the flags.
individual PFx pin to function as an interrupt to the pro-
cessor. Similar to the flag control registers that are used to
set and clear individual flag values, one flag interrupt mask
register sets bits to enable an interrupt function, and the
other flag interrupt mask register clears bits to disable an
UART Clock Rate
SCLK
/16) bits per second.
=
---------------------------------------------- -
16 UART_Divisor
Pin Descriptions on Page
u
®
f
SCLK
) serial infrared physi-
SCLK
/1,048,576) bits per
Rev. C | Page 10 of 64 | December 2007
17).
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF561 processor provides two parallel peripheral
interfaces (PPI0, PPI1) that can connect directly to parallel A/D
and D/A converters, video encoders and decoders, and other
general-purpose peripherals. The PPI consists of a dedicated
input clock pin, up to 3 frame synchronization pins, and up to
16 data pins. The input clock supports parallel data rates at up to
f
as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-
tional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data, and are programmable in the
PPI_CONTROL register.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF561 processors control
when to read from the video source(s). PPI_FS1 is an HSYNC
output and PPI_FS2 is a VSYNC output.
SCLK
• Flag interrupt sensitivity registers – These registers specify
• Input mode – frame syncs and data are inputs into the PPI.
• Frame capture mode – frame syncs are outputs from the
• Output mode – frame syncs and data are outputs from the
/2 MHz, and the synchronization signals can be configured
interrupt function. PFx pins defined as inputs can be con-
figured to generate hardware interrupts, while output PFx
pins can be configured to generate software interrupts.
whether individual PFx pins are level- or edge-sensitive
and specify, if edge-sensitive, whether just the rising edge
or both the rising and falling edges of the signal are signifi-
cant. One register selects the type of sensitivity, and one
register selects which edges are significant for edge
sensitivity.
PPI, but data are inputs.
PPI.