adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 8

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371/ADSP-21375
The SDRAM controller address, data, clock, and command pins
can drive loads up to 30 pF. For larger memory systems, the
SDRAM controller external buffer timing should be selected
and external buffering should be provided so that the load on
the SDRAM controller pins does not exceed 30 pF.
Table 4. External Memory for Non SDRAM Addresses
Table 5. External Memory for SDRAM Addresses
Note that the external memory bank addresses shown are for
normal word accesses. If 48-bit instructions are placed in any
such bank (with two instructions packed into three 32-bit loca-
tions), then care must be taken to map data buffers in the same
bank. For example, if 2k instructions are placed starting at the
bank 0 base address (0x0020 0000), then the data buffers can be
placed starting at an address that is offset by 3k words
(0x0020 0C00).
Asynchronous Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory con-
trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfac-
ing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.
The asynchronous memory controller is capable of a maximum
throughput of 176 Mbps using a 44 MHz external bus speed.
Other features include 8- to 32-bit and 16- to 32-bit packing and
unpacking, booting from bank select 1, and support for delay
line DMA.
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
14M
16M
16M
16M
Size in
Words
62M
64M
64M
64M
Address Range
0x0020 0000–0x00FF FFFF
0x0400 0000–0x04FF FFFF
0x0800 0000–0x08FF FFFF
0x0C00 0000–0x0CFF FFFF
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
Rev. B | Page 8 of 52 | June 2008
ADSP-21371/ADSP-21375 INPUT/OUTPUT
FEATURES
The ADSP-21371/ADSP-21375 I/O processor provides 32 chan-
nels of DMA (ADSP-21371)/ 6 channels of DMA (ADSP-
21375), as well as an extensive set of peripherals. These include a
20-lead digital applications interface, which controls
The ADSP-21371/ADSP-21375 processor also contains a
14-lead digital peripheral interface, which controls
DMA Controller
The ADSP-21371/ADSP-21375’s on-chip DMA controller
allows data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21371’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
port (PDAP) or the UART. Thirty-two channels of DMA are
available on the ADSP-21371, 16 via the serial ports, eight via
the input data port, two for the UART, two for the SPI interface,
two for the external port, and two for memory-to-memory
transfers. Programs can be downloaded to the ADSP-21371/
ADSP-21375 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Delay Line DMA
The ADSP-21371/ADSP-21375 processors provide delay line
DMA functionality. This allows processor reads and writes to
external delay line buffers (and hence to external memory) with
limited core interaction.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DSP DAI pins
(DAI_P1 to DAI_P20).
Programs make these connections using the signal routing unit
(SRU), shown in
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
• Eight serial ports (ADSP-21371)
• S/PDIF receiver/transmitter (ADSP-21371)
• Four precision clock generators
• Input data port/parallel data acquisition port
• Two general-purpose timers
• Two serial peripheral interfaces
• One universal asynchronous receiver/transmitter (UART)
• An I
(ADSP-21371)
2
C
®
-compatible 2-wire interface
Figure
1.