adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 6

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371/ADSP-21375
ADSP-21371/ADSP-21375 MEMORY
The ADSP-21371/ADSP-21375 processors add the following
architectural features to the SIMD SHARC family core.
On-Chip Memory
The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see
ports single-cycle, independent accesses by the core processor
and I/O processor. The ADSP-21371/ ADSP-21375 memory
architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.
Table 2. ADSP-21371 Internal Memory Space
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 CFFF
Reserved
0x0004 D000–0x0004 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 CFFF
Reserved
0x0005 D000–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 0FFF
Reserved
0x0006 1000–0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 0FFF
Reserved
0x0007 1000–0x0007 FFFF
Table 3 on Page
7). Each memory block sup-
Extended Precision Normal or
Instruction Word (48 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 AAA9
Reserved
0x0008 AAAA–0x0008 FFFF
BLOCK 0 RAM
0x0009 0000–0x0009 1554
Reserved
0x0009 1555–0x0009 FFFF
BLOCK 1 ROM
Reserved
BLOCK 1 RAM
0x000B 0000–0x000B 1554
Reserved
0x000B 1555–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 1554
Reserved
0x000C 1555–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 1554
Reserved
0x000E 1555–0x000F FFFF
0x000A 0000–0x000A AAA9
0x000A AAAA–0x000A FFFF
Rev. B | Page 6 of 52 | June 2008
Normal Word (32 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
BLOCK 0 RAM
0x0009 8000–0x0009 9FFF
Reserved
0x0009 A000–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
BLOCK 1 RAM
0x000B 8000–0x000B 9FFF
Reserved
0x000B A000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 1FFF
Reserved
0x000C 2000–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 1FFF
Reserved
0x000E 2000–0x000F FFFF
The ADSP-21371’s SRAM can be configured as a maximum of
32k words of 32-bit data, 64k words of 16-bit data, 21.3k words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to 1 megabit. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
EXTERNAL MEMORY
The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchro-
nous and/or asynchronous memory devices through the use of
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 3FFF
Reserved
0x0013 4000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 3FFF
Reserved
0x0017 4000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 3FFF
Reserved
0x0018 4000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 3FFF
Reserved
0x001C 4000–0x001F FFFF
Short Word (16 bits)