adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 4

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371/ADSP-21375
GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC
bers of the SIMD SHARC family of DSPs that feature Analog
Devices' Super Harvard Architecture. The ADSP-21371/
ADSP-21375 are source code compatible with the ADSP-2126x,
ADSP-2136x, and ADSP-2116x DSPs as well as with first gener-
ation ADSP-2106x SHARC processors in SISD (single-
instruction, single-data) mode. The ADSP-21371/ADSP-21375
processors are 32-bit/40-bit floating point processors optimized
for high performance automotive audio applications with its
large on-chip SRAM and mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
digital applications interface (DAI).
As shown in the functional block diagram
ADSP-21371/ADSP-21375 processors use two computational
units to deliver a significant performance increase over the pre-
vious SHARC processors on a range of DSP algorithms.
Fabricated in a state-of-the-art, high speed, CMOS process, the
ADSP-21371/ADSP-21375 processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the ADSP-21371/ADSP-21375 processors can per-
form 1.596 GFLOPS running at 266 MHz.
Table 1
ADSP-21371/ ADSP-21375 processors.
Table 1. ADSP-21371/ADSP-21375 Benchmarks (at
266 MHz)
1
The ADSP-21371/ADSP-21375 processors continue SHARC’s
industry-leading standards of integration for DSPs, combining a
high performance 32-bit DSP core with integrated, on-chip sys-
tem features.
The block diagram of the ADSP-21371/ADSP-21375
illustrates the following architectural features:
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)
Divide (y/x)
Inverse Square Root
Assumes two files in multichannel SIMD mode
[3
[4
• Two processing elements, each of which comprises an
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
3] × [3
4] × [4
shows performance benchmarks for the
1]
1]
1
1
®
processors are mem-
on Page
Speed
(at 266 MHz)
1.88 ns
7.5 ns
16.91 ns
30.07 ns
13.1 ns
20.4 ns
1, the
Rev. B | Page 4 of 52 | June 2008
on Page 1
The block diagram of the ADSP-21371/ADSP-21375
also illustrates the following architectural features:
ADSP-21371/ADSP-21375 FAMILY CORE
ARCHITECTURE
The ADSP-21371/ADSP-21375 processors are code compatible
at the assembly level with the ADSP-2136x, ADSP-2126x,
ADSP-21160, and ADSP-21161, and with the first generation
ADSP-2106x SHARC processors. The ADSP-21371/
ADSP-21375 processors share architectural features with the
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC
processors, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21371/ADSP-21375 processors contain two compu-
tational processing elements that operate as a single-instruction,
multiple-data (SIMD) engine. The processing elements are
referred to as PEX and PEY and each contains an ALU, multi-
plier, shifter, and register file. PEX is always active, and PEY
may be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction is exe-
cuted in both processing elements, but each processing element
operates on different data. This architecture is efficient at exe-
cuting math intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
• Two programmable interval timers with external event
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
• JTAG test access port
• DMA controller
• ADSP-21371
• Digital peripheral interface that includes two timers, one
counter capabilities
ADSP-21375)
2 M bit, ADSP-21375)
four precision clock generators (PCG), an S/PDIF-compat-
ible digital audio receiver/transmitter, an input data port
(IDP), eight serial ports, eight serial interfaces, a 20-bit par-
allel input port (PDAP), and a flexible signal routing unit
(DAI SRU).
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
—
Digital applications interface that includes
on Page 1