adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 7

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Table 3. ADSP-21375 Internal Memory Space
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asyn-
chronous device types. Non SDRAM external memory address
space is shown in
External Memory Execution
In the ADSP-21371/ADSP-21375, the program sequencer can
execute code directly from external memory bank 0 (SRAM,
SDRAM). This allows a reduction in internal memory size,
thereby reducing the die area. With external execution, pro-
grams run at slower speeds since 48-bit instructions are fetched
in parts from a 16-bit external bus coupled with the inherent
latency of fetching instructions from SDRAM. Fetching instruc-
tions from external memory generally takes 1.5 peripheral clock
cycles per instruction.
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 3FFF
Reserved
0x0004 4000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 C7FF
Reserved
0x0004 C800–0x0004 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 3FFF
Reserved
0x0005 4000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 C7FF
Reserved
0x0005 C800–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 07FF
Reserved
0x0006 0800–0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 07FF
Reserved
0x0007 0800–0x0007 FFFF
Table
4.
Extended Precision Normal or
Instruction Word (48 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 5554
Reserved
0x0008 5555–0x0008 FFFF
BLOCK 0 RAM
0x0009 0000–0x0009 0AAA
Reserved
0x0009 0AAB–0x0009 FFFF
BLOCK 1 ROM
Reserved
BLOCK 1 RAM
0x000B 0000–0x000B 0AAA
Reserved
0x000B 0AAB–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 0AAA
Reserved
0x000C 0AAB–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 0AAA
Reserved
0x000E 0AAB–0x000F FFFF
0x000A 0000–0x000A 5554
0x000A 5555–0x000A FFFF
Rev. B | Page 7 of 52 | June 2008
Normal Word (32 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 7FFF
Reserved
0x0008 8000–0x0009 7FFF
BLOCK 0 RAM
0x0009 8000–0x0009 8FFF
Reserved
0x0009 9000–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000–0x000A 7FFF
Reserved
0x000A 8000–0x000B 7FFF
BLOCK 1 RAM
0x000B 8000–0x000B 8FFF
Reserved
0x000B 9000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 0FFF
Reserved
0x000C 1000–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 0FFF
Reserved
0x000E 1000–0x000F FFFF
SDRAM Controller
The SDRAM controller provides an interface to up to four sepa-
rate banks of industry-standard SDRAM devices or DIMMs.
Fully compliant with the SDRAM standard, each bank can has
its own memory select line (MS0–MS3), and can be configured
to contain between 16M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the
different banks.
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide or as
32 bits wide.
ADSP-21371/ADSP-21375
Short Word (16 bits)
BLOCK 0 ROM
0x0010 0000–0x0010 FFFF
Reserved
0x0011 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 1FFF
Reserved
0x0013 2000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0014 FFFF
Reserved
0x0015 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 1FFF
Reserved
0x0017 2000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 1FFF
Reserved
0x0018 2000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 1FFF
Reserved
0x001C 2000–0x001F FFFF
Table
5.