kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 30

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

Revision History
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
12/23/08
7/30/08
12/5/08
DATE
REVISION
FN6807.0 Converted to intersil template. Assigned
FN6807.1 P1; revised Key Specs
Rev 1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
Initial Release of Production Datasheet
file number FN6807. Rev 0 - first release
(as preliminary datasheet) with new file
number.
P2; added Part Marking column to Order
Info
P4; moved Thermal Resistance to
Thermal Info table and added Theta JA
Note 3 per packaging
P4-6; revisions throughout spec tables.
Removed note from Elec Specs (Nap
Mode must be invoked using SPI.) Added
notes 9 and 10 to Switching Specs.
P9; revised function for Pin 22
OUTMODE, Pin 23 NAPSLP and Pin 70
OUTFMT
P11; revised function for Pin 16 NAPSLP
P13-15; Performance curves revised
throughout
P17; User Initiated Reset - revised 2nd
sentence of 1st paragraph
P19; Nap/Sleep - revised 1st and 2nd
sentences of 2nd paragraph
P23; Address 0x24: Gain_Fine; added 2
sentences to end of 1st paragraph.
Revised Table 8
P22; Serial Peripheral Interface- 1st
paragraph; revised 2nd and 4th
sentences.
P24; removed Figure (PHASE SLIP:
CLK÷2 MODE, fCLOCK = 500MHz)
Address 0x71: Phase_slip; added
sentence to end of paragraph
P27; revised Fig 45
P27; Table 16; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil
standards
30
CHANGE
KAD5512P
January 16, 2009
FN6807.1