KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet

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... These adjustments allow the user to minimize spurs associated with the interleaving process. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P-50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C). ...

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... KAD5512P-50Q72 KAD5512P-50 Q72EP-I NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

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... Analog Input ............................................................... 14 Clock Input ................................................................. 15 Jitter............................................................................ 16 Voltage Reference...................................................... 16 Digital Outputs ............................................................ 16 Over Range Indicator ................................................. 16 Power Dissipation....................................................... 16 Nap/Sleep................................................................... 16 Data Format ............................................................... 17 3 KAD5512P-50 Serial Peripheral Interface ........................................... 19 SPI Physical Interface................................................ 19 SPI Configuration....................................................... 19 Device Information ..................................................... 20 Indexed Device Configuration/Control ....................... 20 Global Device Configuration/Control.......................... 21 Device Test ................................................................ 22 SPI Memory Map ....................................................... 23 Equivalent Circuits ....................................................... 24 Layout Considerations ...

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... AVDD OVDD IAVDD I 3mA LVDS OVDD PSRR 30MHz, 200mV P-P P 3mA LVDS DNL INL f MIN S f MAX S = -1dBFS 500MSPS. SAMPLE KAD5512P-50 MIN TYP MAX 1.40 1.47 1.54 500 1.9 90 -10.0 ±2.0 10.0 ±2.0 435 535 635 0.9 1.8 1.7 1.8 1.9 1.7 1.8 1.9 171 178 68 76 -36 432 460 148 163 ...

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... 995MHz IN SFDR f = 10MHz 105MHz 190MHz 364MHz 695MHz 995MHz IN IMD f = 70MHz 170MHz IN WER FPBW OVDD = -1dBFS 500MSPS. (Continued) SAMPLE KAD5512P-50 MIN TYP MAX 65.9 63.6 65.9 65.8 65.5 64.4 63.2 65.7 63.2 65.7 65.7 65.7 59.8 50.0 10.6 10.2 10.6 10.6 10.5 9.7 8.0 87.3 70 82.0 78 75.2 61.3 50.0 -91.3 -90.6 -12 10 1.3 specifications apply for 10pF load on each digital January 16, 2009 ...

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... Output Rise Time Output Fall Time Timing Diagrams SAMPLE N INP INN t A CLKN CLKP LATENCY = L CYCLES t CPD CLKOUTN CLKOUTP D[11:0]P DATA DATA N-L N-L+1 D[11:0]N FIGURE 1. LVDS TIMING DIAGRAM 6 KAD5512P-50 CONDITIONS MIN ...

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... The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V advised to float the inputs, tie to ground or AVDD depending on desired function. 8. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. 7 KAD5512P-50 CONDITION SYMBOL t A ...

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... ORN, ORP [NC, OR OUTFMT Exposed Paddle NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection) 8 KAD5512P-50 AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground Analog Input Negative, Positive VCM Common Mode Output Tri-Level Clock Divider Control Clock Input True, Complement ...

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... DNC 5 DNC 6 AVDD 7 AVSS 8 AVSS 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5512P-50 KAD5512P-50 (72 LD QFN) TOP VIEW FIGURE 3. PIN CONFIGURATION D8P 53 D8N 52 D7P ...

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... SNR 65 60 300 325 350 375 400 SAMPLE RATE (MSPS) FIGURE 8. SNR AND SFDR KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 600 ...

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... CODE FIGURE 14. NOISE HISTOGRAM 11 KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° (Continued) 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 320 380 440 ...

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... SINAD = 50.0dBFS -40 -60 -80 -100 -120 0 50 100 FREQUENCY (MHz) FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz 12 KAD5512P-50 All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° (Continued) -100 -120 150 200 250 FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz ...

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... The KAD5512P-50 does not have the ability to adjust timing skew mismatches as part of the internal calibration sequence. Clock routing to each unit ADC is carefully matched, however ...

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... OVDD the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P-50 changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...

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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P-50 is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 40), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...

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... The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512P-50 is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...

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... BINARY GRAY CODE FIGURE 31. BINARY TO GRAY CODE CONVERSION 17 KAD5512P-50 Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next MODE lower bit as shown in Figure 32. Normal GRAY CODE Sleep Nap MODE Offset Binary BINARY FIGURE 32 ...

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... CSB SCLK SDIO CSB SCLK SDIO R CSB SCLK SDIO INSTRUCTION/ADDRESS CSB SCLK SDIO INSTRUCTION/ADDRESS 18 KAD5512P-50 A12 A11 A10 FIGURE 33. MSB-FIRST ADDRESSING A11 A12 W0 W1 R/W D0 FIGURE 34. LSB-FIRST ADDRESSING A12 A11 A10 FIGURE 35. INSTRUCTION/ADDRESS PHASE ...

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... The SPI port operates in a half duplex master/slave configuration, with the KAD5512P-50 functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three wire mode ...

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... Scale (0xFF) +133LSB (+47mV) Nominal Step Size 1.04LSB (0.37mV) 20 KAD5512P-50 ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of +/- 4.2%. ( ‘ ...

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... FIGURE 38. PHASE SLIP: CLK÷2 MODE KAD5512P-50 ADDRESS 0X72: CLOCK_DIVIDE The KAD5512P-50 has a selectable clock divider that can be set to divide by two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input” on page 15). This functionality can be overridden and controlled through the SPI, as shown in Table 12 ...

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... KAD5512P-50 ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. ...

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... Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved 74 output_mode_B 75 config_status 76-BF reserved 23 KAD5512P-50 TABLE 17. SPI MEMORY MAP Bit 6 Bit 5 Bit 4 Bit 3 LSB Soft First Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # ...

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... F 1 FIGURE 40. ANALOG INPUTS AVDD AVDD Ω 75kO AVDD Ω 75kO 280O Ω INPUT Ω 75kO FIGURE 42. TRI-LEVEL DIGITAL INPUTS 24 KAD5512P-50 TABLE 17. SPI MEMORY MAP (Continued) Bit 6 Bit 5 Bit 4 Bit 3 [1: Off 1 = Midscale 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved ...

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... The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best 25 KAD5512P-50 OVDD D[11:0]P D[11:0]N DATA + – ...

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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 KAD5512P-50 Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC ...

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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 27 KAD5512P- 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF C 72X 0.60 NOTES: 1. Dimensions are in millimeters. Dimensions ...