kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 26

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

SPI Memory Map
26-5F
60-6F
76-BF
(Hex)
03-07
11-1F
Addr
00
01
02
08
09
10
20
21
22
23
24
25
70
71
72
73
74
75
device_index_A
output_mode_A
output_mode_B
offset_coarse
gain_medium
config_status
chip_version
gain_coarse
port_config
Parameter
phase_slip
offset_fine
burst_end
gain_fine
reserved
reserved
reserved
reserved
reserved
reserved
reserved
chip_id
modes
Name
(MSB)
Active
26
Bit 7
SDO
other codes = reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
DLL Range
LSB First
1 = slow
0 = fast
Result
Bit 6
XOR
clock_divide
Reserved
TABLE 16. SPI MEMORY MAP
Reset
Bit 5
Soft
KAD5512P
Burst end address [7:0]
Reserved
Reserved
Enable
Chip Version #
Result
Coarse Offset
Bit 4
Medium Gain
DDR
XOR
Fine Offset
Reserved
Reserved
Reserved
Fine Gain
Reserved
Reserved
Reserved
Reserved
Chip ID #
Bit 3
Mirror
Coarse Gain
(bit5)
Bit 2
Power-Down Mode [2:0]
001 = Twos Complement
001 = Normal Operation
other codes = reserved
other codes = reserved
other codes = reserved
Output Format [2:0]
100 = Offset Binary
Clock Divide [2:0]
000 = Pin Control
000 = Pin Control
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
010 = Gray Code
100 = Sleep
Mirror
010 = Nap
(bit6)
Bit 1
ADC00
(LSB)
Mirror
Clock
Edge
Bit 0
(bit7)
Next
affected by
affected by
affected by
affected by
Def. Value
Read Only
Soft Reset
Soft Reset
Soft Reset
Soft Reset
Read only
Read only
cal. value
cal. value
cal. value
cal. value
cal. value
(Hex)
NOT
NOT
NOT
NOT
00h
00h
00h
00h
00h
00h
00h
00h
January 16, 2009
Indexed/
Global
FN6807.1
G
G
G
G
G
G
G
G
G
I
I
I
I
I
I
I