kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet
kad5512p-21q72ep-i
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kad5512p-21q72ep-i Summary of contents
Page 1
... Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates 250MSPS. The KAD5512P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset ...
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... Ordering Information PART NUMBER KAD5512P-25Q72 (Note 2) KAD5512P-25 Q72EP-I KAD5512P-21Q72 (Note 2) KAD5512P-21 Q72EP-I KAD5512P-17Q72 (Note 2) KAD5512P-17 Q72EP-I KAD5512P-12Q72 (Note 2) KAD5512P-12 Q72EP-I KAD5512P-25Q48 (Note 1) KAD5512P-25 Q48EP-I KAD5512P-21Q48 (Note 1) KAD5512P-21 Q48EP-I KAD5512P-17Q48 (Note 1) KAD5512P-17 Q48EP-I KAD5512P-12Q48 (Note 1) KAD5512P-12 Q48EP-I NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Analog Input ................................................................ 17 Clock Input .................................................................. 18 Jitter ............................................................................. 19 Voltage Reference....................................................... 19 Digital Outputs ............................................................. 19 Over Range Indicator .................................................. 19 Power Dissipation ........................................................ 19 Nap/Sleep.................................................................... 19 Data Format ................................................................ 20 3 KAD5512P Serial Peripheral Interface ........................................... 22 SPI Physical Interface................................................ 22 SPI Configuration....................................................... 22 Device Information ..................................................... 23 Indexed Device Configuration/Control ....................... 23 Global Device Configuration/Control.......................... 24 Device Test ................................................................ 25 SPI Memory Map ....................................................... 26 Equivalent Circuits ....................................................... 27 Layout Considerations ...
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... Maximum Conversion Rate (per SAMPLE KAD5512P-17 KAD5512P-12 TYP MAX MIN TYP MAX UNITS 1.47 1.54 1.40 1.47 1.54 1000 1000 1.8 1 ppm/°C -10 ±2 10 -10 ±2 10 ±0.6 ±0.6 535 635 435 535 635 0.9 0.9 1.8 1.8 1.7 1.8 1.9 1.7 1.8 1 ...
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... Maximum Conversion Rate (per SAMPLE KAD5512P-17 KAD5512P-12 TYP MAX MIN TYP MAX -36 -36 237 253 219 235 204 189 -0.8 ±0.3 0.8 -0.8 ±0.3 0.8 -2.0 ±1.1 2.0 -2.5 ±1.4 2 170 125 66.9 67.1 65.0 66.9 65.2 67.1 66.7 66.8 66.1 66.1 64.4 64.1 62.7 62.4 66.8 66.3 64.3 65.8 64.3 66.3 65.5 65.6 64.7 64.1 57.9 57.4 48.3 49.3 10.6 10.7 10.5 10 ...
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... 3mA Mode T V 3mA Mode -500µ 1mA Maximum Conversion Rate (per SAMPLE KAD5512P-17 KAD5512P-12 TYP MAX MIN TYP MAX UNITS 78.8 79 81.8 82.0 78.2 71.8 61.6 61.6 49.2 50.3 -94.5 -95.1 dBFS -91.6 -85.7 dBFS -12 - 1.3 1.3 GHz MIN TYP ...
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... FIGURE 2A. DDR Switching Specifications PARAMETER ADC OUTPUT Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode (Note 10) Output Clock to Data Propagation Delay, CMOS Mode (Note 10) 7 KAD5512P CLKN CLKP CLKOUTN CLKOUTP D[11/0]P ODD BITS EVEN BITS ODD BITS D[11/0]N FIGURE 1 ...
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... The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. 8 KAD5512P CONDITION SYMBOL L t ...
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... Exposed Paddle NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection). 9 KAD5512P LVDS [LVCMOS] NAME AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground VINN, VINP Analog Input Negative, Positive VCM Common Mode Output CLKDIV ...
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... DNC 5 DNC 6 AVDD 7 AVSS 8 AVSS 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5512P KAD5512P (72 LD QFN) TOP VIEW FIGURE 3. PIN CONFIGURATION D8P 53 D8N 52 D7P ...
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... SCLK 46 SDIO Exposed Paddle AVSS NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection). 11 KAD5512P 1.8V Analog Supply DNC Do Not Connect Analog Ground Analog Input Negative, Positive VCM Common Mode Output Clock Input True, Complement Tri-Level Power Control (Nap, Sleep modes) ...
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... Pinout AVDD 1 DNC 2 3 DNC 4 DNC AVSS 5 6 VINN 7 VINP 8 AVSS AVDD 9 VCM 10 DNC 11 AVSS 12 12 KAD5512P KAD5512P (48 LD QFN) TOP VIEW FIGURE 4. PIN CONFIGURATION D4P 35 D4N 34 D3P 33 D3N 32 CLKOUTP ...
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... SNR 100 130 160 SAMPLE RATE (MSPS) FIGURE 9. SNR AND SFDR KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). -50 -55 -60 -65 -70 -75 -80 ...
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... CODE FIGURE 15. NOISE HISTOGRAM 14 KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 1.5 1.0 0.5 0 DDR -0.5 -1.0 -1.5 160 ...
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... FREQUENCY (MHz) FIGURE 21. TWO-TONE SPECTRUM @ 70MHz 15 KAD5512P All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 0 -20 -40 -60 -80 -100 -120 0 80 ...
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... Theory of Operation Functional Description The KAD5512P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges ...
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... OVDD the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...
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... This dual transformer scheme is used to improve commonHmode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P is 1000Ω. ADT1-1WT ADT1-1WT 1000pF 0.1µF FIGURE 28 ...
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... The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... BINARY GRAY CODE FIGURE 33. BINARY TO GRAY CODE CONVERSION 20 KAD5512P Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 34. GRAY CODE MODE Normal Sleep Nap BINARY FIGURE 34. GRAY CODE TO BINARY CONVERSION ...
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... CSB SCLK SDIO CSB SCLK SDIO R CSB SCLK SDIO INSTRUCTION/ADDRESS CSB SCLK SDIO INSTRUCTION/ADDRESS 21 KAD5512P A12 A11 A10 FIGURE 35. MSB-FIRST ADDRESSING A11 A12 W0 W1 R/W D0 FIGURE 36. LSB-FIRST ADDRESSING A12 A11 A10 FIGURE 37. INSTRUCTION/ADDRESS PHASE ...
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... The SPI port operates in a half duplex master/slave configuration, with the KAD5512P functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three-wire mode ...
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... Scale (0xFF) +133LSB (+47mV) Nominal Step Size 1.04LSB (0.37mV) 23 KAD5512P ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of +/- 4.2%. ( ‘ ...
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... SLIP TWICE FIGURE 40. PHASE SLIP: CLK÷4 MODE, f ADDRESS 0X72: CLOCK_DIVIDE The KAD5512P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input” on page 18). This functionality can be overridden and ...
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... KAD5512P ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. ...
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... Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved 74 output_mode_B DLL Range 75 config_status 76-BF reserved 26 KAD5512P TABLE 16. SPI MEMORY MAP Bit 6 Bit 5 Bit 4 Bit 3 LSB First Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # ...
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... FIGURE 42. ANALOG INPUTS AVDD AVDD Ω 75kO AVDD Ω 75kO 280O Ω INPUT Ω 75kO FIGURE 44. TRI-LEVEL DIGITAL INPUTS 27 KAD5512P TABLE 16. SPI MEMORY MAP (Continued) Bit 6 Bit 5 Bit 4 Bit Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved Reserved ...
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... Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. 28 KAD5512P OVDD D[11:0]P D[11:0]N DATA + – FIGURE 48. VCM_OUT OUTPUT ...
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... Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. 29 KAD5512P Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused signal superimposed on the power supply voltage. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 30 KAD5512P CHANGE FN6807.1 January 16, 2009 ...
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... Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/08 7.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 5.60 Sq TYPICAL RECOMMENDED LAND PATTERN 31 KAD5512P Exp. DAP 7.00 5.60 Sq. 25 0.90 Max 44X 0.50 C 48X 0.25 48X 0.60 NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSEY14.5m-1994. ...
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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 32 KAD5512P 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF C 72X 0.60 NOTES: 1. Dimensions are in millimeters. Dimensions ...