stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 9

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

across the 2R
device without external circuitry.
Feeding voltage polarity can be reversed in both
soft and hard ways under software command.
4.3.2.3 - Boost Battery
To supply very long lines (high loop resistance),
the SLIC can be set in "Boost battery" mode. In
this mode the line is fed with a total battery volt-
age equal to |Vb+| + |Vb-|, keeping the same cur-
rent limiting values as in active mode. The Vb+
battery is the same positive supply voltage
needed for ringing generation.
4.3.3 - RING
In this mode COFISLIC provides ringing signal
equivalent to a maximum 85Vrms ring line volt-
age. HV L3000N and L3000S handle a maximum
65Vrms balanced ring signal; HV STLC3170 han-
dles a maximum 85Vrms. It is possible to reduce
power consumption if Power Reduced Ring mode
is chosen. The output impedance is represented
only by the two Rp protection resistors and the
current is limited to 100mA.
C/I and CR1 register configuration (programmed
by GCI monitor channel) define Ring conditions
as herebelow shown:
Table 6:
(*) CR1.3 has to be equal to CR1.2 : 0 or 1
If unbalanced ringing is requested, SLIC can sup-
port also external ringing injection configuration,
providing both logic command for relay driver and
ringing detection circuitry.
4.3.3.1 - Ring Generation
When the ringing function is selected, a low level
ringing signal (1.5Vrms typ.) is generated inside
the STLC3040 and provided on the VOUT pin.
This signal is then amplified and injected in bal-
anced mode into the line through the HV
(L3000N, L3000S, STLC3170), with superim-
posed DC voltage of 24V typical. Both ringing fre-
quency and amplitude are software programma-
ble.
The first and the last ring cycles are synchronized
by the STLC3040 so that the ringing signal al-
ways starts and stops with zero phase.
In Ring mode the Off Hook indication is asserted
whenever during two consecutive ring periods ( or
an equivalent time in pause) the mean value of
the IT current exceedes the programmed thresh-
old. After the persistance time the Off Hook is
SLIC MODE
RING
Reduced Power
Ring
p
. Filtering is performed inside the
C/I
(7)
1
1
C/I
(6)
1
0
C/I
(5)
X
X
CR1
(7)
X
X
CR1(*)
1/0
1/0
(3)
CR1(*)
1/0
1/0
(2)
sent to C/I upstream.
4.3.3.2 - Power Reduced Ring
The modes in Table 6 differ only during the ring-
pause phase.
During the pause of reduced-power-ring mode the
SLIC Kit is set in Stand-By.
The pause state is forced by stop ring command
(C/I.5 downstream = 0) or by the detection of Off-
Hook.
4.3.3.3 - Unbalanced Ringing
The device allows an unbalanced Ring applica-
tion. This application requires an external ringing
generator. A digital I/O pin can be used to drive
the external relay driver.
An external ring sync. signal synchronised on the
Vring zero crossing, must be provided on pin 29
of STLC3040. The external ring frequency must
be the same as the value programmed in the in-
ternal register.
4.4 - TESTING FEATURES
STLC3040/HV (L3000N, L3000S, STLC3170) kit
allows to perform up to 11 tests. They are aimed
at covering the following issues.
1. Line and Battery Characteristics AC, DC
2. SLIC Kit block testing.
3. Signal Path Behavior
Every test is set by internal registers, which are
written through GCI data down Monitor.
Test results are typically digitalized, codified and
dropped in the first PCM channel (byte B1) of GCI
interface. For four go/nogo tests (Analog Loop-
back, Ring Generator, TTX Generator and TTX
filter) the result of the test is also written in one bit
of CR5 register that is readable through Monitor.
Test functions are carried out with SLIC Kit in a
mode set automatically by COFISLIC. For detailed
explanation about tests see chapter 6.
4.4.2 - Loop Backs
LOOP1 and LOOP2 bits of CR4 register set up
some internal loop backs. This feature is typically
used for COFISLIC tests (see fig. 3).
Any Loopback is enabled by CR1.5 bit. Loopback
type is selected by register CR4.
There are three types of loopback.
Loopback 1 (CR4.2 = 0, CR4.1 = 1) simply copies
the downstream B1 to the upstream B1 through
the GCI interface. In this case no Rx signal is sent
to the line. The kit operates as previously set.
Loopback 2 (CR4.2 = 1, CR4.1 = 0) sets Kit SLIC
in Active mode. It copies the output of DSD (Digi-
tal Sigma Delta converter) to the input of the DEC
Leakage.
STLC3040
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