stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 17

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

Table 9:
Data transfer is completed by the next byte:
4.7.1.1 TOP Command
As above mentioned TOP command allows read-
ing Signalling Register and Coefficient RAM
checksum.
R/W = 0 No Operation
In answer to TOP command COFISLIC will place
the Start byte first.
Coefficient checksum is defined by this algorithm:
This algorithm guarantees a fault coverage of:
(1 - 2
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2
BIT7
LSEL1
X
1
0
0
1
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
IDH
0V
0V
0V
0V
0V
0V
0V
0V
-15
= 1 Read Operation
BIT6
R/W
)
0
LSEL0
X
BIT5 BIT4
0
1
0
16
X
0
IDM
+5V
+5V
+5V
+5V
-5V
-5V
-5V
-5V
-5V
-5V
0V
0V
0V
0V
0V
0V
X
1 byte for signalling register
reading
1 byte for signalling register and
2 bytes for filter coefficients
checksum reading, low byte is
read first and then high byte.
15 bytes for Line Card
Identification Code reading
10
X
0
X
BIT3 BIT2
1
7
1
+5V
+5V
+5V
+5V
IDL
-5V
-5V
-5V
-5V
-5V
-5V
0V
0V
0V
0V
0V
0V
X
1
0
1
LSEL1 LSEL0
BIT1
BIT1
Id. Code
0
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
BIT0
BIT0
0
SIGNALLING REGISTER (SR)
SR provides information about loop condition:
Off/OnHook condition, line constant current, line
voltage. It also signals temperature alarm related
to HV SLIC (L3000N, L3000S, STLC3170) and
clock fails (see page 10). The Clock fail indication
is set whenever the number of DCL periods in
one frame (between two-FSC pulses) is different
from the standard one.
Hook and Ground Key state variations toggle the
related bits of SR register and therefore switch
HOOK and GNDK bits of upstream C/I.
Every change of any of the six most significative
bits of SR register is summarized in SLCX bit (bit
5) of upstream Command/Indicate, provided that
these bits are not masked by CR12 register.
Masking acts only on SLCX bit.
Reset Value: 00h
HOOK indicates loop condition (same as in up-
stream C/I):
GNDK shows a Ground Key detection (same as
in upstream C/I):
VB_2 half battery voltage across the line is detected
(V
This bit is designed to indicate the line DC operat-
ing point only in Stand-By and Active modes, with
no TTX injection
where: |V
ILIM Current Limit Region
This interrupt is automatically masked in Ringing
Mode
TEMP Temperature alarm of HV SLIC (L3000N,
L3000S, STLC3170) which is signalled through
HV (L3000N, L3000S, STLC3170) interface
HOOK GNDK
BIT7 BIT6 BIT5 BIT4 BIT3
= 0 Subscriber is On-Hook
= 1 Subscriber is Off-Hook
= 0 No Detected Longitudinal Current
= 1 Detected Longitudinal Current
= 0 if (|V
= 1 if (|V
= 0 Resistive Feeding Region
= 1 Constant Current Feeding Region
= 0 Normal Temperature
LINE
compared to
|V
LINE
OL
LINE
LINE
| = |V
VB_2 ILIM TEMP
| = |V
|<|
|>|
V
V
BAT
2
2
OL
OL
TIP
V
-V
|)
|)
2
OL
- V
DROP
).
RING
|
|
CK_FAIL
BIT2
STLC3040
BIT1 BIT0
XX
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XX