stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 10

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

STLC3040
block, as shown in fig. 3. Rx signal goes on to the
line. Please note that this loopback function cuts
off the Tx channel connection to the line.
All other functionalities are those of Active mode.
Loopback 3 (CR4.2 = 1, CR4.1 = 1) sets Kit SLIC
in Active mode. Rx signal is prevented to go the
line. Tx path is cut off from the line as well. Output
of ASD is copied to input of AFE port filter. DSP
part can be still exercised via B1. All the function-
alities are those of active mode.
4.4.3 - Test Tones Generation
In Active mode STL3040 can generate either
1kHz or 800Hz frequencies towards the 2-wire
line. The two tones can also be enabled at the
same time.
TON bit of CR1 register enables the 1 kHz test
tone generator. 800Hz is enabled by CR5[3.0] =
4h.
800Hz amplitude is programmable through the
same register (CR10) used to set TTX amplitude.
1kHz level is fixed at PCM full scale and can be
modified changing Rx channel gain.
4.5 COFISLIC Reset
Any reset to COFISLIC sets SLIC kit in External
Indication. COFISLIC is set in Power denial.
There are four different reset sources:
During Reset, output pins are set as follows:
Additionally a Reset of the DSP part of the
COFISLIC is triggered by CLK fail detection (see
also page 17).
4.5.1.1 Power On Reset
When voltage at VDD pin crosses over an internal
fixed threshold (typ. 2.5V) COFISLIC is reset.
4.5.1.2 Reset Pin MR
If an high level is applied to pin 36 (MR) the
COFISLIC is reset.
MR pin has built-in filter to reduce spike sensitiv-
ity. Spikes smaller than 90ns are neglected.
Therefore at MR pin a high level is surely recog-
nised as a Reset if it is present for at least 2 s.
10/49
DU
C1
C2
PDO
O1
Power-On Reset,
Reset pin MR (pin 36),
Reset bit (SOP command bit 4).
(pin 6)
(pin 9)
(pin 10)
(pin 28)
( pin 39)
High impedance
V
V
High impedance
Low Level
hv
hv
4.5.1.3 Reset bit RST (SOP command bit 4)
If RST bit is programmed to 1 COFISLIC is reset.
SOP register is set by GCI down stream channel.
Until the end of the current command processing,
the GCI is kept active.
4.5.1.4 - CLK fail Reset
Clock fail triggers a reset routine of the DSP
which lasts, until the first good frame that follows
the failed ones.
In active mode during the Reset routine, the voice
channel of "Data up" (Du, pin 6) is forced IDLE
dependent on the selected codification law.
As far as "Data down" (DD, pin 5) is concerned,
the voice channel does not reach the Vout during
this phase.
Z sinthesys is partially performed, the DSP
branch is not active while the analog loop is kept
active.
Coefficients and CR registers’ contents do not
change because of this partial reset, GCI state as
well. Metering pulse injection signaling is not af-
fected too. Ring generation and ring trip detection
are not influenced too.
4.5.2. Start-up State
During reset the device is in Power- Denial Mode.
After Reset, COFISLIC is automatically switched
to its basic start-up state in which it uses internal
default values for all filters and settings (AC and
DC).
Programmed coefficients of filters are not reset.
Bit 0 of CR6 register, FIXC, is set to 1, this means
that fixed values are used after a Reset until FIXC
is set to 0.
Even if FIXC = 1, both checksum and reading of
filter coefficients are carried out on formerly pro-
grammed coefficient set.
Table 7: Fixed Filter Coefficients
SLIC is switched to operating mode carried by
GCI Command Indicate at least two frames after
reset. SLIC status and Filter configuration can be
changed by SOP and COP commands.
After reset the device is internally set as follows:
KA, KD
Filter
- configuration registers are set to their default
GTX
GRX
R
Z
X
B
0E00
019C, 24A0, 1600
149A, 0521, 3F40,3EF2
1879, 39E0, 00B4,0006
FF
60
0, 0, 0, 0050, 0680, 06D0, 0, 3C80
Coefficients (h)