stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 11

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

– DC characteristics of SLIC-Kit
AC characteristics of SLIC-Kit
Further after the reset
- RST bit (SOP command bit 4) is set to 1 to in-
- GCI interface is reset. After software Reset its
- DU is in high impedance state
- FIXC = 1 (CR6 Register) Fixed Coefficients
- External Indication
- Normal Battery
- Test Disabled
- Persistence for Off-Hook and I1: 10ms
- Persistence for Ground Key: 20ms
- Ring Trip threshold = 4.2mA
- Ilim = 22mA in active mode
- Ilim = 7.7mA in Stand-By mode
- Off-Hook detection threshold in active mode =
- Off-Hook detection threshold in Stand-By
- Feeding Resistance in either Active or Stand-
- Ring: Internal
- Ring Frequency = 25Hz
- Ring Voltage = 65Vrms
- Line Voltage Drop = 28.2V
- External Indication Voltage Threshold for Off-
- A-law is programmed
- Metering with Teletax
- Line Impedance: (Synthetized Impedance + 2
- Balance Impedance: 910 / / 62nF
- Tx Gain: 0dBr
- Rx Gain: -7dBr
- Teletax Voltage onto line V
- Teletax Frequency = 16kHz
- Battery Reversal: Hard
- I/O pins are set as inputs
- PD bit of CR1 is reset (means STLC3040 in
- All bits of Signalling Register are masked
- Data Upstream C/I byte is reset to 0
values (see Chapter 4-8 Configuration Regis-
ter)
dicate that a reset has occured
former state is kept. On-going GCI communi-
cation is stopped
are selected
10mA
mode = 7.7mA
By mode = 2
value is not included)
Hook detection = 9.0V
Power-Denial mode).
Rp) = 700 + 2Rp
(50 + Rp) (fuse impedance
TTX
= 10Vrms
Check Configuration-registers reset-value for
more detailed information.
4.6 GCI Backplane Interface
GCI is a standard serial interface for interconnec-
tion of SLIC kit to the line card backplane.
The digital interface is used to transfer status in-
formation to and from the SLIC as well as to
transfer filter coefficients for the DSP.
With this approach an analog Line Card could be
replaced by an ISDN one and viceversa without
need to change the interface to the linecard con-
troller.
As far as physical level is concerned this standard
consists of four wires:
The frame is divided into eight time-slots which
contains four bytes each. Bit rate in both direc-
tions is 2048Kbit/sec and it’s not affected by clock
frequency. This can be chosen setting SEL24 pin.
Eight GCI time slots are selectable via three pins
TS2-TS0 (see Table 8).
For every time slot the first bit, received or trans-
mitted, is the Most Significant one, according to
timing diagram shown in fig. 7.
Information is clocked out on the rising edge of
data clock and it is latched in on the falling edge
of DCL signal.
Frame Synchronization FSC is a 8KHz signal and
its rising edge gives the time reference of the first
bit in the first GCI (input or output) channel and
resets the slot counter at the next falling edge of
the clock every frame.
Four bytes of any GCI time slot are:
A single GCI channel has 256kbit/s data rate.
Exchange Protocol
STLC3040 validates a received byte if it is detected
identical two consecutive times. (see figg. and 7and 8)
The exchange protocol is identical for both direc-
tions. The sender uses the E bit to indicate that it
is sending a Monitor byte while the receiver uses
A bit to acknowledge the received byte. When no
Byte 1
8bits
- Serial Transmitted data to the backplane: DU
- Serial Received data from the backplane: DD
- 8KHz Frame Synchronization: FSC
- Master Data Clock (2048KHz or 4096KHz): DCL
- B1 channel for PCM data,
- B2 channel not used,
- M (Monitor) channel used to write and monitor
- C/I (Command/Indication) channel used to set
B1
COFISLIC internal registers,
the Operating Mode.
Byte 2
8bits
B2
MONITOR
Byte 3
8bits
6bits
C/I
1bit
Byte 4
A
STLC3040
1bit
11/49
E