s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 138

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Serial Communications Interface (ESCI) Module
Receiving a break character has these effects on ESCI registers:
13.4.2.4 Idle Characters
For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or
parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle
character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
13.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in ESCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values including idle, break, start, and stop bits, are inverted when TXINV is at 1. See
13.8.1 ESCI Control Register
13.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the ESCI transmitter:
13.4.3 Receiver
Figure 13-5
13.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
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Sets the framing error bit (FE) in SCS1
Sets the ESCI receiver full bit (SCRF) in SCS1
Clears the ESCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
ESCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the ESCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
shows the structure of the ESCI receiver.
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
1.
Freescale Semiconductor