s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 90

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Configuration Register (CONFIG)
MCLKSEL — MCLK Source Select Bit
MCLK1 and MCLK0 — MCLK Output Select Bits
TMBCLKSEL— Timebase Clock Select Bit
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
SCIBDSRC — SCI Baud Rate Clock Source Bit
90
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS pin to be used as a MCLK output clock.
Once configured for MCLK, the PTD data direction register for PTD0 is used to enable and disable the
MCLK output. See
TMBCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See
detailed description of the external clock operation.
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module
the rest of the MCU stops. See
cease to generate clocks while in stop mode. The default state for this option is clear, disabling the
oscillator in stop mode.
SCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See
Communications Interface (ESCI)
1 = Crystal frequency
0 = Bus frequency
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
1 = Oscillator enabled during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal data bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
Address:
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$001E
Table 5-1
Bit 7
0
0
MCLK1
Figure 5-1. Configuration Register 2 (CONFIG2)
0
0
1
1
= Unimplemented
MCLKSEL
for MCLK options.
6
0
Chapter 16 Timebase Module
Table 5-1. MCLK Output Select
Module.
(CGM). This function is used to keep the timebase running while
MCLK1
MCLK0
5
0
0
1
0
1
MCLK0
R
4
0
= Reserved
Chapter 16 Timebase Module (TBM)
MCLK Frequency
MCLK not enabled
Clock divided by 2
Clock divided by 4
R
3
0
Clock
TMBCLKSEL OSCENINSTOP SCIBDSRC
(TBM). When clear, the oscillator will
Chapter 13 Enhanced Serial
2
0
1
0
Freescale Semiconductor
Bit 0
1
for a more