s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 217

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.12 I/O Registers
Three registers control and monitor SPI operation:
15.12.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
Freescale Semiconductor
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
1. X = Don’t care
SPE
Address: $0010
0
1
1
1
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
SPMSTR
X
SPRIE
Bit 7
(1))
0
1
1
R
0
Figure 15-14. SPI Control Register (SPCR)
= Reserved
MODFEN
R
6
0
Table 15-2. SPI Configuration
X
X
0
1
SPMSTR
5
1
Master without MODF
SPI Configuration
Master with MODF
CPOL
Not enabled
4
0
Slave
CPHA
3
1
SPWOM
2
0
General-purpose I/O;
General-purpose I/O;
Function of SS Pin
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
SPE
1
0
SPTIE
Bit 0
0
I/O Registers
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