s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 196

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
Interrupt Status Register 4
Bits 7–2 — Always read 0
IF24–IF23 — Interrupt Flags 24–23
14.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
14.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output (see
Module
to the break interrupt subsection of each module to see how each module is affected by the break state.
14.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
14.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
196
These flags indicate the presence of an interrupt request from the source shown in
1 = Interrupt request present
0 = No interrupt request present
(TIM2)). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer
Address:
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$FE07
Bit 7
R
R
0
0
Figure 14-15. Interrupt Status Register 4 (INT4)
Chapter 17 Timer Interface Module (TIM1)
= Reserved
R
6
0
0
R
5
0
0
R
4
0
0
R
3
0
0
R
2
0
0
and
Chapter 18 Timer Interface
IF24
R
1
0
Freescale Semiconductor
Bit 0
IF23
Table
R
0
14-3.