sg2567rdr212451ib ETC-unknow, sg2567rdr212451ib Datasheet - Page 5

• Manufacturer Part Number: sg2567rdr212451ib
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

Pin Description Table (Contd.)
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Symbol
A0~A9,
A10/AP,
A11~A13
DQ0~DQ63
CB0~CB7
DQS0~DQS17
DQS0#~DQS17#
SA0~SA2
SDA
SCL
RESET#
PAR_IN
ERR_OUT#
V
V
V
V
V
NC
DU
DD
SS
REF
DDQ
DDSPD
Type
Input
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input
Input
Input
Output
Supply
Supply
Supply
Supply
Supply
-
-
Polarity
-
-
Positive
Edge
Negative
Edge
-
-
-
Active Low
-
-
-
-
-
-
-
-
-
Function
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-
CA9, CA11) when sampled at the rising clock edge. In addition to the column address,
A10/AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge. The address inputs also provide the op-code during Mode Register Set com-
mands.
Data and Check Bit Input/Output pins.
DDR2 SDRAM differential data strobe for input and output data.
DDR2 SDRAM differential data strobe for input and output data.
Slave Address Select for EEPROM. These pins are used to configure the presence-detect
device.
Serial Bus Data Line for EEPROM. SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module. A resistor must be con-
nected from the SDA bus line to V
Serial Bus Clock for EEPROM. SCL is used to synchronize the presence-detect data trans-
fer to and from the module. A resistor may be connected from the SCL bus line to V
act as pull up on the system board.
Register and PLL control pin. When low, all register outputs will be driven low and the PLL
clocks to the DRAM and register will be set to low levels (the PLL will remain synchronized
with the input clock, if within spec range).
Parity bit for the Address and Control bus. (“1”: Odd, “0”: Even)
Parity error found in the Address and Control bus.
SDRAM positive power supply. 1.8V±0.1V
Power supply return (ground).
SDRAM I/O reference supply.
SDRAM I/O Driver positive power supply. 1.8V±0.1V
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports operation from 1.7V to 3.6V).
No Connect.
Do not use.
DD
to act as pull up on the system board.
SG2567RDR212451UU
October 16, 2007
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