sg2567rdr212451ib ETC-unknow, sg2567rdr212451ib Datasheet - Page 19

• Manufacturer Part Number: sg2567rdr212451ib
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

OCD Default Output Characteristics
(V
Notes:
1. Absolute specifications: 0°C ≤ T
2. Impedance measurement condition for output source DC current: V
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and volt-
4. Output slew rate for falling and rising edges is measured between V
5. The absolute value of the slew rate as measured from V
6. This represents the step size when the OCD is near 18Ω at nominal conditions across all process and repre-
7. Timing skew due to DRAM output slew rate mis-match between DQS/DQS# and associated DQs is included in
Output Slew Rate Load Diagram
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Parameter
Output Impedance
Pull-up and Pull-down mismatch
Output Slew Rate
Output Step Size for Calibration
DD
V
surement condition for output sink DC current: V
23.4Ω for values of V
age.
ended signals. For differential signals output slew rate is measured between DQS - DQS# = -500mV and
DQS# - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each
device.
the slew rate as measured from V
tion.
sent only the DRAM uncertainty.
t
DQSQ
DDQ
= 1.8V±0.1V, V
)/I
and t
OH
must be less than 23.4Ω for values of V
QHS
Output
(V
specification.
OUT
SS
)
OUT
= 0V, T
between 0V and 280mV.
A
case
= 0 to +6
V
IL
TT
25Ω
(AC) max to V
≤ +85°C; V
Symbol
S
5°C)
OUT
Reference Point
DDQ
DDQ
IH
OUT
= +1.8V±0.1V, V
(AC) min. This is guaranteed by design and characteriza-
= 1.7V; V
IL
between V
12.6
Min
1.5
(DC) max to V
0
0
OUT
SG2567RDR212451UU
DDQ
DDQ
= 280mV; V
TT
Nom
DD
18
- 250mV and V
IH
and V
= 1.7V; V
= +1.8V±0.1V.
(DC) min is equal to or greater than
DDQ
OUT
OUT
Max
23.4
1.5
- 280mV. Impedance mea-
4
5
/I
OL
TT
= 1420mV; (V
must be less than
October 16, 2007
+ 250mV for single
V/ns
Unit
Ω
Ω
Ω
1, 2
1, 2, 3
1, 4, 5, 7
6
OUT
Notes
-
19