sg2567rdr212451ib ETC-unknow, sg2567rdr212451ib Datasheet - Page 20

• Manufacturer Part Number: sg2567rdr212451ib
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

IDD Specification Parameters and Test Conditions
(V
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Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
DD
= 1.8V±0.1V, V
Parameter
Operating one bank active–precharge current; t
t
SWITCHING; Data bus inputs are SWITCHING
Operating one bank active–read–precharge current; I
AL = 0; t
CS# are HIGH between valid commands; Address bus inputs are SWITCHING; Data pat-
tern is same as IDD4W
Precharge power–down current; All banks idle; t
trol and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle; t
HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current; All banks idle; t
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power–down current; All banks open; t
LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Active standby current; All banks open; t
t
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL =
CL(IDD), AL = 0; t
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Operating burst read current; All banks open, Continuous burst reads, I
4, CL = CL(IDD), AL = 0; t
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as IDD4W
Burst refresh current; t
is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, I
CL = CL(IDD), AL = t
t
inputs are STABLE during DESELECTs; Data pattern is same as IDD4R
RASmin(IDD)
RP(IDD)
RCD
= 1*t
; CKE is HIGH, CS# is HIGH between valid commands; Other control and address
CK
CK(IDD)
= t
; CKE and CS# are HIGH between valid commands; Address bus inputs are
CK(IDD),
SS
CK
; CKE is HIGH, CS# is HIGH between valid commands; Address bus
= 0V, T
RCD(IDD)
= t
t
CK(IDD),
RC
CK
CK
= t
= t
A
= t
-1*t
RC(IDD),
CK(IDD)
= 0 to +65°C)
CK(IDD),
t
RAS
CK(IDD)
= t
; Refresh command at every t
t
RAS
RASmax(IDD),
t
; t
RAS
CK
CK
= t
CK
= t
= t
= t
RASmin(IDD),
CK
CK(IDD),
CK(IDD),
= t
RASmax(IDD),
CK
CK
= t
CK
CK(IDD);
CK(IDD);
= t
= t
t
= t
RP
OUT
CK(IDD);
CK(IDD),
CK(IDD);
t
t
RAS
RC
= t
CKE is HIGH, CS# is HIGH;
t
RP(IDD)
= 0mA; BL = 4, CL = CL(IDD),
RCD
= t
CKE is
= t
t
RP
RC(IDD),
CKE is LOW; Other con-
RASmax(IDD),
t
CKE is HIGH, CS# is
= t
RC
= t
RFC(IDD)
; CKE is HIGH, CS# is
RCD(IDD)
RP(IDD)
= t
OUT
RC(IDD),
t
OUT
RRD
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
SG2567RDR212451UU
= 0mA; BL = 4,
; CKE is
interval; CKE
; CKE and
= 0mA; BL =
= t
t
RP
RRD(IDD),
t
RAS
=
=
CL 5.0
2.5ns
5140
5410
2260
2800
3160
3880
3610
4420
6580
6760
8020
8560
216
October 16, 2007
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
20