sg2567rdr212451ib ETC-unknow, sg2567rdr212451ib Datasheet - Page 24

• Manufacturer Part Number: sg2567rdr212451ib
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The refresh period is 64ms. This equates to an average refresh rate of 7.8125μs. However, an REFRESH comand must be asserted at
11. Each byte lane has a corresponding DQS.
12. CK and CK# input slew rate must be ≥ 1 V/ns (≥ 2 V/ns if measured differentially).
13. The data valid window is derived by achieving other specifications: t
14. MIN (t
15. t
16. READs and WRITEs with no auto precharge are allowed to be issued before t
17. V
18. t
19. This is a minimum requirement. Minimum READ to internal PRECHARGE timing is AL + BL/2 providing the t
20. Operating frequency is only allowed to change during self refresh mode or precharge power-down mode. Anytime the operating frequency
21. ODT turn-on time t
22. ODT turn-off time t
23. This parameter has a two clock minimum requirement at any t
24. t
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Command/Address minimum input slew rate = 1.0V/ns and is referenced to the crosspoint of CK/CK#. t
This maximum value is derived from the reference test load. t
The intent of the Don’t Care state after completion of the postamble is the DQS driven signal should be high, low or high-Z and that any
This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic
The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW
[HIGH] level.
for a rising signal and V
ating values for Command/Address input signal slew rates < 1.0V/ns are TBD.
Data minimum input slew rate = 1.0V/ns and is referenced to the crosspoint of DQS/DQS# if differential strobe feature is enabled. t
ing is referenced to V
(DC)
t
voltage level, but specify when the device output is no longer driving (t
t
signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high [above V
then it must not transition low (below V
LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during
his time depending on t
least once every 70.3μs or t
derates in direct proportion to the clock duty cycle and a practical data valid window can be derived.
be greater than the minimum specification limits for t
in DDR2 SDRAM.
tion.
cation clock period; n
been satisfied. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until t
is changed, not including jitter, the DLL is required to be reset followed by 200 clock cycles.
(MAX)
impedence. Both are measured from t
condition.
HZ
LZ (MIN)
HP (MIN)
DAL
DELAY
IL
/V
and t
for a fallng signal. Derating values for Data input signal slew rates < 1.0V/ns are TBD.
= (n
IH
CL
is when the resistance is fully on. Both are measured from t
is calculated from t
DDR2 overshoot/undershoot. Refer to 256MB, 512MB, or 1GB DDR2 SDRAM component data sheet for more detailed informa-
, t
LZ
will prevail over a t
WR
is the lesser of t
CH
transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
) + (t
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
RP
AON (MIN)
AOF (MIN)
/t
IH (AC)
WR
CK
DQSS
IL (AC)
): For each of the terms above, if not already an integer, round to the next highest integer. t
refers to the t
CL
IS
DQSCK (MIN)
RFC (MAX)
for a rising signal and V
minimum and t
.
is when the device starts to turn-off ODT resistance. ODT turn-off time t
+ t
is when the device leaves high impedence and ODT resistance begins to turn-on. ODT turn-on time t
for a fallng signal. t
CK
+ t
IH
AOFD
; issuing more than eight REFRESH commands back to back at t
WR
IH DC
so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system reset
+ t
parameter stored in the MR[11,10,9].
CH
.
RPRE (MAX)
) prior to t
minimum actually applied to the device CK and CK# inputs.
IH
IL (AC)
timing is referenced to V
CL
DQSH(min)
and t
condition.
for a fallng signal. t
CH
HZ (MAX)
CK
).
.
.
AOND
HP,
HZ
will prevail over a t
(t
.
CK
) or begins driving (t
/2), t
IH (DC)
RAS (MIN)
DH
DQSQ
timing is referenced to V
SG2567RDR212451UU
for a rising signal and V
, and t
is satisfied since t
DQSCK (MAX)
QH
LZ
).
(t
QH
AOF (MAX)
= t
RAS (MIN)
HP
IS
RFC (min)
+ t
IH (DC)
RAS
timing is referenced to V
RPST (MAX)
- t
IL (DC)
RTP
QHS
lockout feature is supported
October 16, 2007
is when the bus is in high
for a rising signal and V
has been satisfied.
). The data valid window
and t
is not allowed.
for a fallng signal. Der-
CK
RAS (MIN)
refers to the appli-
condition.
IH DC (MIN)
have
IH (AC)
AON
DS
24
tim-
IL
]