LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 25

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

The timing diagram of Figure 16 was obtained from the
circuit of Figure 15. The CLK was 5MHz for the timing
diagram and the TMS320C25 clock rate was 40MHz.
Figure 17 shows the timing diagram with the LTC1198
running off a 2.7V supply and 5MHz CLK.
TYPICAL
D
D
CLK
CLK
OUT
OUT
D
D
CS
CS
IN
IN
Figure 16. Scope Trace the LTC1198 Running Off
5V Supply in the Circuit of Figure 15
Figure 17. Scope Trace the LTC1198 Running Off
2.7V Supply in the Circuit of Figure 15
A
PPLICATI
NULL
BITS
NULL
BITS
HORIZONTAL: 1500ns/DIV
HORIZONTAL: 500ns/DIV
MSB
(B7)
MSB
(B7)
O
U
(B0)
LSB
S
LSB
(B0)
1196/98 F17
1196/98 F16
Software Description
The software configures and controls the serial port of the
TMS320C25.
The code first sets up the interrupt and reset vectors. On
reset the TMS320C25 starts executing code at the label
INIT. Upon completion of a 16-bit data transfer, an inter-
rupt is generated and the DSP will begin executing code at
the label RINT.
In the beginning, the code initializes registers in the
TMS320C25 that will be used in the transfer routine. The
interrupts are temporarily disabled. The data memory
page pointer register is set to zero. The auxiliary register
pointer is loaded with one and auxiliary register one is
loaded with the value 200 hexadecimal. This is the data
memory location where the data from the LTC1198 will be
stored. The interrupt mask register (IMR) is configured to
recognize the RINT interrupt, which is generated after
receiving the last of 16 bits on the serial port. This interrupt
is still disabled at this time. The transmit framing synchro-
nization pin (FSX) is configured to be an output. The F0 bit
of the status register ST1, is initialized to zero which sets
up the serial port to operate in the 16-bit mode.
Next, the code in TXRX routine starts to transmit and
receive data. The D
shifted left eight times so that it appears as in Figure 18.
This D
respect to CH1. The D
register and the RINT interrupt is enabled. The NOP is
repeated 3 times to mask out the interrupts and minimize
the cycle time of the conversion to be 20 clock cycles. All
clocking and CS functions are performed by the hardware.
B15
IN
Figure 18. D
Circuit in Figure 15
0
word configures the LTC1198 for CH0 with
START
1
IN
S/D
Word in ACC of TMS320C25 for the
IN
0
IN
word is loaded into the ACC and
word is then put in the transmit
O/S
LTC1196/LTC1198
0
DUMMY
0
DUMMY
1
0
L1196/98 F18
B8
0
25