LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 15

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

ADDRESS IN
SHIFT MUX
Connection to a microprocessor or a DSP serial port is
quite simple (see Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196/LTC1198.
Data Transfer
Data transfer differs slightly between the LTC1196 and the
LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK
and D
the LTC1196 Operating Sequence. After CS falls, the first
CLK pulse enables D
conversion result is output on the D
high resets the LTC1196 for the next data exchange.
The LTC1198 can transfer data with 3 or 4 wires. The
additional input, D
configuration.
The data transfer between the LTC1198 and the digital
systems can be broken into two sections: Input Data Word
and A/D Conversion Result. First, each bit of the input data
word is captured on the rising CLK edge by the LTC1198.
Second, each bit of the A/D conversion result on the D
line is updated on the rising CLK edge by the LTC1198.
This bit should be captured on the next rising CLK edge by
the digital systems (see A/D Conversion Result section).
Data transfer is initiated by a falling chip select (CS) signal
as shown in the LTC1198 Operating Sequence. After CS
falls the LTC1198 looks for a start bit. After the start bit is
received, the 4-bit input word is shifted into the D
The first two bits of the input word configure the LTC1198.
The last two bits of the input word allow the ADC to acquire
the input voltage by 2.5 clocks before the conversion
starts. After the conversion starts, two null bits and the
A
PPLICATI
CS
OUT
. A falling CS initiates data transfer as shown in
D
IN1
2 NULL BITS
O
IN
D
OUT1
U
, is used to select the 2-channel MUX
SHIFT A/D CONVERSION
RESULT OUT
OUT
S
. After two null bits, the A/D
I FOR ATIO
U
D
IN2
OUT
W
line. Bringing CS
D
OUT2
U
IN
1196/98 AI01
input.
OUT
Start Bit
The first “logical one” clocked into the D
goes low is the start bit. The start bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the D
Multiplexer (MUX) Address
The 2 bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND.
conversion result are output on the D
of the data exchange CS should be brought high. This
resets the LTC1198 in preparation for the next data ex-
change.
Input Data Word
The LTC1196 requires no D
configured to have a single differential input. The conver-
sion result is output on the D
sequence, followed by zeros indefinitely if clocks are
continuously applied with CS low.
The LTC1198 clocks data into the D
edge of the clock. The input data word is defined as follows:
SINGLE-ENDED
DIFFERENTIAL
MUX MODE
MUX MODE
START
IN
pin are then ignored until the next CS cycle.
LTC1198 Channel Selection
SGL/DIFF
SGL/
DIFF
MUX ADDRESS
1
1
0
0
ADDRESS
MUX
LTC1196/LTC1198
ODD/SIGN
ODD/
SIGN
0
1
0
1
IN
DUMMY
OUT
word. It is permanently
DUMMY
CHANNEL #
0
+
+
–
BITS
IN
line in an MSB-first
DUMMY
OUT
119698 AI02
input on the rising
IN
line. At the end
1
+
–
+
input after CS
1196/98 AI03
GND
–
–
15