LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 23

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

500kHz linear-input bandwidth.
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise floor is extremely
low, corresponding to a transition noise of less than
0.1LSB. DC accuracy includes 0.5LSB total unadjusted
error at 5V. At 3V, linearity error is 0.5LSB while total
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of five when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent perfor-
mance on a 3V rail. With a 3V supply, the LTC1196
converts in 1.6 s, samples at 450kHz, and provides a
unadjusted error increases to 1LSB.
A
PLD Interface Using the Altera EPM5064
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register as shown in Figure 12. The
circuit works as follows: bringing ENA high makes the CS
output high and the EN input low to reset the LTC1196 and
disable the shift register. Bringing ENA low, the CS output
TYPICAL
DATA
CLK
ENA
PPLICATI
Figure 12. An Equivalent Circuit of the EPM5064
A
O
PPLICATI
CLK
ENA
CONVERTER
U
12-BIT
S
I FOR ATIO
CS
U
O
U
SHIFT REGISTER
DATA
CLK
W
EN
S
8-BIT
B0-B7
1196/98 F12
U
B0-B7
CS
Table 1. 5V/3V Performance Comparison
LTC1196-1
P
Max f
Min t
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
LTC1198-1
P
P
Max f
Min t
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
goes high for one CLK cycle with every 12 CLK cycles. The
inverted signal, EN, of the CS output makes the 8-bit data
available on the B0-B7] lines. Figures 13 and 14 show the
interconnection between the LTC1196 and EPM5064 and
the timing diagram of the signals between these two
devices. The CLK frequency in this circuit can run up to
f
CLK(MAX)
DISS
DISS
DISS
–
Figure 13. Intefacing the LTC1196 to the Altera EPM5064 PLD
+
CONV
CONV
SMPL
SMPL
(Shutdown)
1
2
3
4
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
+IN
–IN
GND
CS
of the LTC1196.
LTC1196
D
V
CLK
V
OUT
REF
1 F
CC
8
7
6
5
V
CC
LTC1196/LTC1198
CLK
7.9 at 300kHz
7.9 at 300kHz
750kHz
0.5LSB
0.5LSB
50mW
50mW
31, 32, 43
600ns
600ns
1MHz
1MHz
15 W
1MHz
9-13, 21,
33
23
34
35
5V
ENA
CLK
DATA
3, 14, 25, 36
EPM5064
B7
B0
1196/98 F13
7.9 at 100kHz
7.9 at 100kHz
1
37
38
39
40
41
42
44
383kHz
500kHz
287kHz
500kHz
0.5LSB
0.5LSB
10mW
10mW
1.6 s
1.6 s
23
9 W
3V