LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 20

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

LTC1196/LTC1198
A
“–” Input Settling
At the end of the t
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settle completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R
will improve settling time. If a large “–” input source
resistance must be used, the time allowed for settling can
be extended by using a slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figures 1 and 7). Again, the “+” and “–” input
sampling times can be extended as described above to
accommodate slower op amps.
To achieve the full sampling rate, the analog input should
be driven with a low impedance source (<100 ) or a high
speed op amp (e.g., the LT1223, LT1191, or LT1226).
Higher impedance sources or slower op amps can easily
be accommodated by allowing more time for the analog
input to settle as described above.
Source Resistance
The analog inputs of the LTC1196/LTC1198 look like a
25pF capacitor (C
as shown in Figure 8. C
selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors will slow the settling
of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within t
20
PPLICATI
V
V
IN
IN
–
+
Figure 8. Analog Input Equivalent Circuit
R
R
SOURCE
SOURCE
O
+
–
SMPL
IN
) in series with a 120 resistor (R
U
INPUT
INPUT
“–”
“+”
S
, the input capacitor switches to the
SMPL
IN
I FOR ATIO
U
gets switched between the
.
t
SMPL
t
SMPL
W
120
R
ON
LTC1196
LTC1198
C
25pF
1196/98 F08
U
IN
SOURCE
ON
–
)
REFERENCE INPUT
The voltage on the reference input of the LTC1196 defines
the voltage span of the A/D converter. The reference input
has transient capacitive switching currents which are due
to the switched-capacitor conversion technique (see Fig-
ure 9). During each bit test of the conversion (every CLK
cycle), a capacitive current spike will be generated on the
reference pin by the ADC. These high frequency current
spikes will settle quickly and do not cause a problem if the
reference input is bypassed with at least a 0.1 F capacitor.
The reference input can be driven with standard voltage
references. Bypassing the reference with a 0.1 F capacitor
is recommended to keep the high frequency impedance
low as described above. Some references require a small
resistor in series with the bypass capacitor for frequency
stability. See the individual reference data sheet for details.
Reduced Reference Operation
The minimum reference voltage of the LTC1198 is limited
to 2.7V because the V
nally tied together. However, the LTC1196 can operate
with reference voltages below 1V.
The effective resolution of the LTC1196 can be increased
by reducing the input span of the converter. The LTC1196
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Full-
Scale Error vs Reference Voltage). However, care must be
taken when operating at low values of V
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following factors
must be considered when operating at low V
1. Offset
2. Noise
Figure 9. Reference Input Equivalent Circuit
R
V
OUT
REF
REF
GND
5
4
+
CC
supply and reference are inter-
EVERY CLK CYCLE
R
ON
REF
LTC1196
because of the
5pF TO
30pF
1196/98 F09
REF
values.