MT9042CP1 Zarlink Semiconductor, Inc., MT9042CP1 Datasheet - Page 8

• Manufacturer Part Number: MT9042CP1
• Description: PLL, Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs
• Manufacturer: Zarlink Semiconductor, Inc.

MT9042C
Automatic Control
Automatic Control should be used when simple
MT9042C control is required, which is more complex
than the very simple control provide by Manual
Control with no external circuitry, but not as complex
as Manual Control with a microcontroller.
example, simple control could include operation in a
system which can be accommodated by the
Automatic Control State Diagram shown in Figure 8.
Automatic Control is also selected by mode/control
pins MS2 and MS1. However, the mode and active
reference source is selected automatically by the
internal Automatic State Machine (See Figure 6).
The mode and reference changes are based on the
logic levels on the LOS1, LOS2 and GTi control pins.
Refer to Table 5 and Figure 8 for details of the state
change sequences.
Normal Mode
Normal Mode is typically used when a slave clock
source, synchronized to the network is required.
In Normal Mode, the MT9042C provides timing
(C1.5o, C2o, C3o, C4o, C8o and C16o) and frame
synchronization (F0o, F8o, F16o) signals, which are
synchronized to one of two reference inputs (PRI or
SEC).
nominal frequency of 8kHz, 1.544MHz or 2.048MHz.
From a reset condition, the MT9042C will take up to
25 seconds for the output signal to be phase locked
to the selected reference.
The
dependent as shown in state tables 4 and 5. The
reference frequencies are selected by the frequency
control pins FS2 and FS1 as shown in Table 1.
Holdover Mode
Holdover Mode is typically used for short durations
(e.g., 2 seconds) while network synchronization is
temporarily disrupted.
In Holdover Mode, the MT9042C provides timing and
synchronization signals, which are not locked to an
external reference signal, but are based on storage
techniques. The storage value is determined while
the device is in Normal Mode and locked to an
external reference signal.
8
selection
The input reference signal may have a
of
input
references
is
control
For
When in Normal Mode, and locked to the input
reference signal, a numerical value corresponding to
the MT9042C output frequency is stored alternately
in two memory locations every 30ms.
device is switched into Holdover Mode, the value in
memory from between 30ms and 60ms is used to set
the output frequency of the device.
The frequency accuracy of Holdover Mode is
± 0.05ppm, which translates to a worst case 35 frame
(125us) slips in 24 hours. This exceeds the AT&T
TR62411 Stratum 3 requirement of ± 0.37ppm (255
frame slips per 24 hours).
Two factors affect the accuracy of Holdover Mode.
One is drift on the Master Clock while in Holdover
Mode, drift on the Master Clock directly affects the
Holdover Mode accuracy.
Master Clock (OSCi) accuracy does not affect
Holdover accuracy, only the change in OSCi
accuracy while in Holdover. For example, a ± 32ppm
master clock may have a temperature coefficient of
± 0.1ppm per degree C. So a 10 degree change in
temperature, while the MT9042C is in Holdover
Mode may result in an additional offset (over the
± 0.05ppm) in frequency accuracy of ± 1ppm. Which
is much greater than the ± 0.05ppm of the MT9042C.
The other factor affecting accuracy is large jitter on
the reference input prior
mode switch. For instance, jitter of 7.5UI at 700Hz
may reduce the Holdover Mode accuracy from
0.05ppm to 0.10ppm.
Freerun Mode
Freerun Mode is typically used when a master clock
source is required, or immediately following system
power-up
achieved.
In Freerun Mode, the MT9042C provides timing and
synchronization signals which are based on the
master clock frequency (OSCi) only, and are not
synchronized to the reference signals (PRI and
SEC).
The accuracy of the output clock is equal to the
accuracy of the master clock (OSCi). So if a ± 32ppm
output clock is required, the master clock must also
be ± 32ppm. See Applications - Crystal and Clock
Oscillator sections.
before
network
(30ms to 60ms) to the
Note that the absolute
synchronization
When the
is