MT9042CP1 Zarlink Semiconductor, Inc., MT9042CP1 Datasheet - Page 18

• Manufacturer Part Number: MT9042CP1
• Description: PLL, Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs
• Manufacturer: Zarlink Semiconductor, Inc.

MT9042C
Dual T1 Reference Sources with MT9042C in
Automatic Control
For systems requiring simple state machine control,
the application circuit shown in Figure 14 using
Automatic Control may be used.
In
Automatically, is using a Guard Time Circuit, and the
LOS1 and LOS2 inputs to determine all mode
changes.
about 1s, all line interruptions (LOS1=1) less than 1s
will cause the MT9042C to go from Primary Normal
Mode to Holdover Mode and not switch references.
For line interruptions greater than 1s, the MT9042C
will switch Modes from Holdover to Secondary
Normal, providing the secondary signal is valid
(LOS2=0).
(LOS1=0), the MT9042C will switch back to Primary
Normal Mode.
For complete Automatic Control state machine
details, refer to Table 5 for the State Table, and
Figure 8 for the State Diagram.
18
this
circuit,
Since the Guard Time Circuit is set to
After receiving a good primary signal
the
MT9042C
is
operating
Dual E1 Reference Sources with MT9042B in
Manual Control
For systems requiring complex state machine
control, the application circuit shown in Figure 16
using Manual Control may be used.
In this circuit, the MT9042C is operating Manually
and is using a controller for all mode changes. The
controller sets the MT9042C modes (Normal,
Holdover or Freerun) by controlling the MT9042C
mode/control select pins (MS2 and MS1). The input
(Primary or Secondary) is selected with the
reference select pin (RSEL). TIE correction from
Primary Holdover Mode to Primary Normal Mode is
enabled and disabled with the guard time input pin
(GTi).
re-aligned with the TIE circuit reset pin (TRST), and
a complete device reset is done with the RST pin.
The controller uses two stimulus inputs (LOS)
directly from the MT9075 E1 interfaces, as well as an
external stimulus input.
come from a device that monitors the status registers
of the E1 interfaces, and outputs a logic one in the
event of an unacceptable status condition.
For complete Manual Control state machine details,
refer to Table 4 for the State Table, and Figure 7 for
the State Diagram.
The input to output phase alignment is
The external input may