MT9042CP1 Zarlink Semiconductor, Inc., MT9042CP1 Datasheet - Page 14

• Manufacturer Part Number: MT9042CP1
• Description: PLL, Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs
• Manufacturer: Zarlink Semiconductor, Inc.

MT9042C
CTS CXO-65-HG-5-C-20.0MHz
Frequency:
Tolerance:
Rise & Fall Time:
Duty Cycle:
The output clock should be connected directly (not
AC coupled) to the OSCi input of the MT9042C, and
the OSCo output should be left open as shown in
Figure 9.
Crystal
Oscillator may be used. A complete oscillator circuit
made up of a crystal, resistor and capacitors is
shown in Figure 10.
The accuracy of a crystal oscillator depends on the
crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20MHz crystal specified
with a 32pF load capacitance, each 1pF change in
load capacitance contributes approximately 9ppm to
the frequency deviation.
tolerances, and stray capacitances have a major
effect on the accuracy of the oscillator frequency.
The trimmer capacitor shown in Figure 10 may be
used to compensate for capacitive effects.
accuracy is not a concern, then the trimmer may be
removed, the 39pF capacitor may be increased to
56pF, and a wider tolerance crystal may be
substituted.
The crystal should be a fundamental mode type - not
an overtone. The fundamental mode crystal permits
a simpler oscillator circuit with no additional filter
components and is less likely to generate spurious
responses. The crystal specification is as follows.
Frequency:
Tolerance:
Oscillation Mode:
Resonance Mode:
14
1uH inductor: may improve stability and is optional
MT9042C
Figure 10 - Crystal Oscillator Circuit
Oscillator
OSCo
OSCi
1MΩ
-
56pF
20MHz
25ppm 0C to 70C
8ns (0.5V 4.5V 50pF)
45% to 55%
Alternatively,
100Ω
Consequently, capacitor
20MHz
20MHz
As required
Fundamental
Parallel
39pF
1uH
a
3-50pF
Crystal
If
Load Capacitance:
Maximum Series Resistance:
Approximate Drive Level:
e.g., CTS R1027-2BB-20.0MHZ
(
Guard Time Adjustment
AT&T TR62411 recommends that excessive switching
of the timing reference should be minimized. And that
switching between references only be performed when
the primary signal is degraded (e.g., error bursts of 2.5
seconds).
Minimizing switching (from PRI to SEC) in the
MT9042C can be realized by first entering Holdover
Mode for a predetermined maximum time (i.e., guard
time). If the degraded signal returns to normal before
the expiry of the guard time (e.g., 2.5 seconds), then
the MT9042C is returned to its Normal Mode (with no
reference switch taking place).
reference input may be changed from Primary to
Secondary.
A simple way to control the guard time (using
Automatic Control) is with an RC circuit as shown in
Figure 11. Resistor R
limits the current flowing into the GTi pin during
power down conditions.
calculated as follows.
•
±
20ppm absolute,
V
GTi Schmitt Trigger input, see DC Electrical
Characteristics
SIH
MT9042C
Figure 11 - Symmetrical Guard Time Circuit
is the logic high going threshold level for the
guard time
guard time RC 0.6
example
guard time 150k 10u
GTo
GTi
±
6ppm 0C to 50C, 32pF, 25
≈
≈
=
150kΩ
RC
R
P
×
is for protection only and
×
×
The guard time can be
ln
1kΩ
R



P
--------------------------------
V DD V SIH
32pF
35
1mW
×
Ω
+
0.6
V DD
10uF
–
=
Otherwise, the
C
0.9s
Ω



)