MT9042CP1 Zarlink Semiconductor, Inc., MT9042CP1 Datasheet - Page 2

• Manufacturer Part Number: MT9042CP1
• Description: PLL, Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs
• Manufacturer: Zarlink Semiconductor, Inc.

MT9042C
2
Pin Description
Pin #
1,15
5,18
10
11
12
13
14
2
3
4
6
7
8
9
Name
OSCo
TRST
C1.5o
OSCi
F16o
SEC
F0o
F8o
C3o
C2o
C4o
V
PRI
V
DD
SS
Ground. 0 Volts.
TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a re-alignment of input phase with output phase as shown in
Figure 19. The TRST pin should be held low for a minimum of 300ns.
Secondary Reference (TTL Input). This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of three possible frequencies (8kHz,
1.544MHzMHz, or 2.048MHz) may be used. The selection of the input reference is based
upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual).
Primary Reference (TTL Input). See pin description for SEC.
Positive Supply Voltage. +5V
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left
unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected
from this pin to OSCo, see Figure 10. For clock oscillator operation, this pin is connected to a
clock source, see Figure 9.
Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 16.384Mb/s. See Figure 20.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.
Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS operation at
8.192Mb/s. See Figure 20.
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Clock 3.088MHz (CMOS Output). This output is used in T1 applications.
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
OSCo
C1.5o
OSCi
F16o
VDD
F0o
F8o
Figure 2 - Pin Connections
12 13 14 15 16 17 18
10
11
5
4
6
7
8
9
Description (see notes 1 to 5)
DC
3 2
nominal.
1
28
27
19
25
24
23
22
21
20
26
RSEL
MS1
MS2
LOS1
LOS2
GTo
GTi