CY28439 SpectraLinear, CY28439 Datasheet - Page 13

• Manufacturer Part Number: CY28439
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 21, 2006
Manual Recovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the N value as programmed by the user in
the N recovery register, and the M value that is stored in the
Recovery M register (not accessible by the user) should be
restored. The current M value should be latched into the M
recovery register by the WD_EN bit being set.
No Recovery
If no recovery mode is selected, in the event of a Watchdog
time out, the device should just assert the SRESET# and keep
the current values of M and N.
Software Reset
Software reset is a reset function which is used to send out a
pulse from SRESET# pin. It is controlled by the SW_RESET
enable register bit. Upon completion of the byte/word/block
write in which the SW_RESET bit was set, the device will send
a RESET pulse on the SRESET# pin. The duration of the
SRESET# pulse should be the same as the duration of the
SRESET# pulse after a Watchdog timer time out.
After the SRESET# pulse is asserted the SW_RESET bit
should be automatically cleared by the device.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
PD
Figure 4. Power-down Assertion Timing Waveform
PD (Power-down)—Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition
within 4 clock periods. When the SMBus PD drive mode bit
corresponding to the differential (CPU, SRC, and DOT) clock
output of interest is programmed to ‘0’, the clock output is held
with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#”
tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note the
example below shows CPUT = 133 MHz and PD drive mode
= ‘1’ for all differential outputs. This diagram and description is
applicable to valid CPU frequencies 100, 133, 166, 200, 266,
333, and 400 MHz. In the event that PD mode is desired as
the initial power-on state, PD must be asserted HIGH in less
than 10 s after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up.
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CY28439
Page 13 of 21